]> git.ipfire.org Git - thirdparty/linux.git/commitdiff
Merge branch 'for-next/mte' into for-next/core
authorWill Deacon <will@kernel.org>
Fri, 2 Oct 2020 11:16:11 +0000 (12:16 +0100)
committerWill Deacon <will@kernel.org>
Fri, 2 Oct 2020 11:16:11 +0000 (12:16 +0100)
Add userspace support for the Memory Tagging Extension introduced by
Armv8.5.

(Catalin Marinas and others)
* for-next/mte: (30 commits)
  arm64: mte: Fix typo in memory tagging ABI documentation
  arm64: mte: Add Memory Tagging Extension documentation
  arm64: mte: Kconfig entry
  arm64: mte: Save tags when hibernating
  arm64: mte: Enable swap of tagged pages
  mm: Add arch hooks for saving/restoring tags
  fs: Handle intra-page faults in copy_mount_options()
  arm64: mte: ptrace: Add NT_ARM_TAGGED_ADDR_CTRL regset
  arm64: mte: ptrace: Add PTRACE_{PEEK,POKE}MTETAGS support
  arm64: mte: Allow {set,get}_tagged_addr_ctrl() on non-current tasks
  arm64: mte: Restore the GCR_EL1 register after a suspend
  arm64: mte: Allow user control of the generated random tags via prctl()
  arm64: mte: Allow user control of the tag check mode via prctl()
  mm: Allow arm64 mmap(PROT_MTE) on RAM-based files
  arm64: mte: Validate the PROT_MTE request via arch_validate_flags()
  mm: Introduce arch_validate_flags()
  arm64: mte: Add PROT_MTE support to mmap() and mprotect()
  mm: Introduce arch_calc_vm_flag_bits()
  arm64: mte: Tags-aware aware memcmp_pages() implementation
  arm64: Avoid unnecessary clear_user_page() indirection
  ...

22 files changed:
1  2 
arch/arm64/Kconfig
arch/arm64/include/asm/cpucaps.h
arch/arm64/include/asm/cpufeature.h
arch/arm64/include/asm/hwcap.h
arch/arm64/include/asm/kvm_arm.h
arch/arm64/include/asm/memory.h
arch/arm64/include/asm/pgtable-prot.h
arch/arm64/include/asm/pgtable.h
arch/arm64/include/asm/processor.h
arch/arm64/include/asm/sysreg.h
arch/arm64/kernel/Makefile
arch/arm64/kernel/cpufeature.c
arch/arm64/kernel/cpuinfo.c
arch/arm64/kernel/entry.S
arch/arm64/kernel/hibernate.c
arch/arm64/kernel/process.c
arch/arm64/kernel/signal.c
arch/arm64/kernel/suspend.c
arch/arm64/kvm/sys_regs.c
arch/arm64/mm/Makefile
arch/arm64/mm/fault.c
arch/arm64/mm/ptdump.c

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index 88f160afc468b39b410a4cd33b8eda4dc2c020bb,5fb9b728459b884f2bb24378c403dda765e74f17..bbaf0bc4ad60966ea35a730aa5a746355fdcf424
@@@ -57,8 -59,10 +57,9 @@@ arm64-reloc-test-y := reloc_test_core.
  obj-$(CONFIG_CRASH_DUMP)              += crash_dump.o
  obj-$(CONFIG_CRASH_CORE)              += crash_core.o
  obj-$(CONFIG_ARM_SDE_INTERFACE)               += sdei.o
 -obj-$(CONFIG_ARM64_SSBD)              += ssbd.o
  obj-$(CONFIG_ARM64_PTR_AUTH)          += pointer_auth.o
  obj-$(CONFIG_SHADOW_CALL_STACK)               += scs.o
+ obj-$(CONFIG_ARM64_MTE)                       += mte.o
  
  obj-y                                 += vdso/ probes/
  obj-$(CONFIG_COMPAT_VDSO)             += vdso32/
index 79207c3235530de83dc58dbb4a574973c698c836,add9da5d8ea34075b8023ac40ff508c9f6b73dd4..dcc165b3fc046b8573a579f04dd3e71474c7c471
@@@ -227,7 -228,9 +228,9 @@@ static const struct arm64_ftr_bits ftr_
  static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = {
        ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_MPAMFRAC_SHIFT, 4, 0),
        ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_RASFRAC_SHIFT, 4, 0),
 -      ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SSBS_SHIFT, 4, ID_AA64PFR1_SSBS_PSTATE_NI),
+       ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_MTE),
+                      FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_MTE_SHIFT, 4, ID_AA64PFR1_MTE_NI),
 +      ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SSBS_SHIFT, 4, ID_AA64PFR1_SSBS_PSTATE_NI),
        ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_BTI),
                                    FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_BT_SHIFT, 4, 0),
        ARM64_FTR_END,
index 25113245825c0b16c1181c6e01cbbe05b52a63d5,6104b87f021dca3a46603af1b1fc37812cd333a8..6a7bb3729d605dd50281794b9563010f71e50385
@@@ -43,56 -43,58 +43,57 @@@ static const char *icache_policy_str[] 
  unsigned long __icache_flags;
  
  static const char *const hwcap_str[] = {
 -      "fp",
 -      "asimd",
 -      "evtstrm",
 -      "aes",
 -      "pmull",
 -      "sha1",
 -      "sha2",
 -      "crc32",
 -      "atomics",
 -      "fphp",
 -      "asimdhp",
 -      "cpuid",
 -      "asimdrdm",
 -      "jscvt",
 -      "fcma",
 -      "lrcpc",
 -      "dcpop",
 -      "sha3",
 -      "sm3",
 -      "sm4",
 -      "asimddp",
 -      "sha512",
 -      "sve",
 -      "asimdfhm",
 -      "dit",
 -      "uscat",
 -      "ilrcpc",
 -      "flagm",
 -      "ssbs",
 -      "sb",
 -      "paca",
 -      "pacg",
 -      "dcpodp",
 -      "sve2",
 -      "sveaes",
 -      "svepmull",
 -      "svebitperm",
 -      "svesha3",
 -      "svesm4",
 -      "flagm2",
 -      "frint",
 -      "svei8mm",
 -      "svef32mm",
 -      "svef64mm",
 -      "svebf16",
 -      "i8mm",
 -      "bf16",
 -      "dgh",
 -      "rng",
 -      "bti",
 -      "mte",
 -      NULL
 +      [KERNEL_HWCAP_FP]               = "fp",
 +      [KERNEL_HWCAP_ASIMD]            = "asimd",
 +      [KERNEL_HWCAP_EVTSTRM]          = "evtstrm",
 +      [KERNEL_HWCAP_AES]              = "aes",
 +      [KERNEL_HWCAP_PMULL]            = "pmull",
 +      [KERNEL_HWCAP_SHA1]             = "sha1",
 +      [KERNEL_HWCAP_SHA2]             = "sha2",
 +      [KERNEL_HWCAP_CRC32]            = "crc32",
 +      [KERNEL_HWCAP_ATOMICS]          = "atomics",
 +      [KERNEL_HWCAP_FPHP]             = "fphp",
 +      [KERNEL_HWCAP_ASIMDHP]          = "asimdhp",
 +      [KERNEL_HWCAP_CPUID]            = "cpuid",
 +      [KERNEL_HWCAP_ASIMDRDM]         = "asimdrdm",
 +      [KERNEL_HWCAP_JSCVT]            = "jscvt",
 +      [KERNEL_HWCAP_FCMA]             = "fcma",
 +      [KERNEL_HWCAP_LRCPC]            = "lrcpc",
 +      [KERNEL_HWCAP_DCPOP]            = "dcpop",
 +      [KERNEL_HWCAP_SHA3]             = "sha3",
 +      [KERNEL_HWCAP_SM3]              = "sm3",
 +      [KERNEL_HWCAP_SM4]              = "sm4",
 +      [KERNEL_HWCAP_ASIMDDP]          = "asimddp",
 +      [KERNEL_HWCAP_SHA512]           = "sha512",
 +      [KERNEL_HWCAP_SVE]              = "sve",
 +      [KERNEL_HWCAP_ASIMDFHM]         = "asimdfhm",
 +      [KERNEL_HWCAP_DIT]              = "dit",
 +      [KERNEL_HWCAP_USCAT]            = "uscat",
 +      [KERNEL_HWCAP_ILRCPC]           = "ilrcpc",
 +      [KERNEL_HWCAP_FLAGM]            = "flagm",
 +      [KERNEL_HWCAP_SSBS]             = "ssbs",
 +      [KERNEL_HWCAP_SB]               = "sb",
 +      [KERNEL_HWCAP_PACA]             = "paca",
 +      [KERNEL_HWCAP_PACG]             = "pacg",
 +      [KERNEL_HWCAP_DCPODP]           = "dcpodp",
 +      [KERNEL_HWCAP_SVE2]             = "sve2",
 +      [KERNEL_HWCAP_SVEAES]           = "sveaes",
 +      [KERNEL_HWCAP_SVEPMULL]         = "svepmull",
 +      [KERNEL_HWCAP_SVEBITPERM]       = "svebitperm",
 +      [KERNEL_HWCAP_SVESHA3]          = "svesha3",
 +      [KERNEL_HWCAP_SVESM4]           = "svesm4",
 +      [KERNEL_HWCAP_FLAGM2]           = "flagm2",
 +      [KERNEL_HWCAP_FRINT]            = "frint",
 +      [KERNEL_HWCAP_SVEI8MM]          = "svei8mm",
 +      [KERNEL_HWCAP_SVEF32MM]         = "svef32mm",
 +      [KERNEL_HWCAP_SVEF64MM]         = "svef64mm",
 +      [KERNEL_HWCAP_SVEBF16]          = "svebf16",
 +      [KERNEL_HWCAP_I8MM]             = "i8mm",
 +      [KERNEL_HWCAP_BF16]             = "bf16",
 +      [KERNEL_HWCAP_DGH]              = "dgh",
 +      [KERNEL_HWCAP_RNG]              = "rng",
 +      [KERNEL_HWCAP_BTI]              = "bti",
++      [KERNEL_HWCAP_MTE]              = "mte",
  };
  
  #ifdef CONFIG_COMPAT
index aeb337029d567410419f718658f116ec0c7cd33c,ff34461524d4cd70270442a61aee5679cb218af3..f30007dff35f7eb89eb8aa5e7e8eb34fa75f009e
@@@ -145,8 -146,35 +145,34 @@@ alternative_cb   spectre_v4_patch_fw_miti
        nop                                     // Patched to SMC/HVC #0
  alternative_cb_end
  .L__asm_ssbd_skip\@:
 -#endif
        .endm
  
+       /* Check for MTE asynchronous tag check faults */
+       .macro check_mte_async_tcf, flgs, tmp
+ #ifdef CONFIG_ARM64_MTE
+ alternative_if_not ARM64_MTE
+       b       1f
+ alternative_else_nop_endif
+       mrs_s   \tmp, SYS_TFSRE0_EL1
+       tbz     \tmp, #SYS_TFSR_EL1_TF0_SHIFT, 1f
+       /* Asynchronous TCF occurred for TTBR0 access, set the TI flag */
+       orr     \flgs, \flgs, #_TIF_MTE_ASYNC_FAULT
+       str     \flgs, [tsk, #TSK_TI_FLAGS]
+       msr_s   SYS_TFSRE0_EL1, xzr
+ 1:
+ #endif
+       .endm
+       /* Clear the MTE asynchronous tag check faults */
+       .macro clear_mte_async_tcf
+ #ifdef CONFIG_ARM64_MTE
+ alternative_if ARM64_MTE
+       dsb     ish
+       msr_s   SYS_TFSRE0_EL1, xzr
+ alternative_else_nop_endif
+ #endif
+       .endm
        .macro  kernel_entry, el, regsize = 64
        .if     \regsize == 32
        mov     w0, w0                          // zero upper 32 bits of x0
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index 584c14ce3c860d814cbf60658e2dec9aba0f701a,62c239cd60c27c4cd3d22fb7d1943576842740eb..96cd347c7a4651597fa2459d4256188134792c1c
@@@ -72,7 -73,11 +73,10 @@@ void notrace __cpu_suspend_exit(void
         * have turned the mitigation on. If the user has forcefully
         * disabled it, make sure their wishes are obeyed.
         */
 -      if (arm64_get_ssbd_state() == ARM64_SSBD_FORCE_DISABLE)
 -              arm64_set_ssbd_mitigation(false);
 +      spectre_v4_enable_mitigation(NULL);
+       /* Restore additional MTE-specific configuration */
+       mte_suspend_exit();
  }
  
  /*
index 7b8a8f6169d06f0d7a28ed7e58264af23a19b5e1,379f4969d0bd7e8338cb2c9792f485f9026ec94d..9ca270603980869b10ec09c112a8ee55b881844f
@@@ -1131,9 -1131,8 +1131,11 @@@ static u64 read_id_reg(const struct kvm
                if (!vcpu_has_sve(vcpu))
                        val &= ~(0xfUL << ID_AA64PFR0_SVE_SHIFT);
                val &= ~(0xfUL << ID_AA64PFR0_AMU_SHIFT);
 +              if (!(val & (0xfUL << ID_AA64PFR0_CSV2_SHIFT)) &&
 +                  arm64_get_spectre_v2_state() == SPECTRE_UNAFFECTED)
 +                      val |= (1UL << ID_AA64PFR0_CSV2_SHIFT);
+       } else if (id == SYS_ID_AA64PFR1_EL1) {
+               val &= ~(0xfUL << ID_AA64PFR1_MTE_SHIFT);
        } else if (id == SYS_ID_AA64ISAR1_EL1 && !vcpu_has_ptrauth(vcpu)) {
                val &= ~((0xfUL << ID_AA64ISAR1_APA_SHIFT) |
                         (0xfUL << ID_AA64ISAR1_API_SHIFT) |
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