dt-bindings: clock: add Mobileye EyeQ6L/EyeQ6H clock indexes

Add #defines for Mobileye EyeQ6L and EyeQ6H SoC clocks.

Constant prefixes are:
 - EQ6LC_PLL_: EyeQ6L clock PLLs
 - EQ6HC_SOUTH_PLL_: EyeQ6H south OLB PLLs
 - EQ6HC_SOUTH_DIV_: EyeQ6H south OLB divider clocks
 - EQ6HC_ACC_PLL_: EyeQ6H accelerator OLB PLLs

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
Link: https://lore.kernel.org/r/20241007-mbly-clk-v5-2-e9d8994269cb@bootlin.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/include/dt-bindings/clock/mobileye,eyeq5-clk.h b/include/dt-bindings/clock/mobileye,eyeq5-clk.h
index 26d8930335e4b113a74f47575957e39163f02766..b433c1772c28fae818b3a6ba428d1f89000f9206 100644 (file)
--- a/include/dt-bindings/clock/mobileye,eyeq5-clk.h
+++ b/include/dt-bindings/clock/mobileye,eyeq5-clk.h
@@ -19,4 +19,25 @@
 
 #define EQ5C_DIV_OSPI  10
 
+#define EQ6LC_PLL_DDR          0
+#define EQ6LC_PLL_CPU          1
+#define EQ6LC_PLL_PER          2
+#define EQ6LC_PLL_VDI          3
+
+#define EQ6HC_SOUTH_PLL_VDI            0
+#define EQ6HC_SOUTH_PLL_PCIE           1
+#define EQ6HC_SOUTH_PLL_PER            2
+#define EQ6HC_SOUTH_PLL_ISP            3
+
+#define EQ6HC_SOUTH_DIV_EMMC           4
+#define EQ6HC_SOUTH_DIV_OSPI_REF       5
+#define EQ6HC_SOUTH_DIV_OSPI_SYS       6
+#define EQ6HC_SOUTH_DIV_TSU            7
+
+#define EQ6HC_ACC_PLL_XNN              0
+#define EQ6HC_ACC_PLL_VMP              1
+#define EQ6HC_ACC_PLL_PMA              2
+#define EQ6HC_ACC_PLL_MPC              3
+#define EQ6HC_ACC_PLL_NOC              4
+
 #endif