S/390: Fix mode in vector merge pattern.

vec_unpacks_hi_v4sf/vec_unpacks_lo_v4sf expand vec_mergeh and vec_mergel
patterns also for z13 with V4SF modes so the patterns should better
accept this.  Fixed by changing the mode iterator to V_128_NOSINGLE
which accepts V4SF unconditionally.

gcc/ChangeLog:

2017-10-04  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* config/s390/vx-builtins.md ("vec_mergeh<mode>")
	("vec_mergel<mode>"): Change mode iterator to V_128_NOSINGLE.

From-SVN: r253420

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 5167a14788fc503303e589de56b03adf66965352..d8a9bc1e75b0c1ec7af6c63f19c60c0cc9eea503 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2017-10-04  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
+
+       * config/s390/vx-builtins.md ("vec_mergeh<mode>")
+       ("vec_mergel<mode>"): Change mode iterator to V_128_NOSINGLE.
+
 2017-10-04  Wilco Dijkstra  <wdijkstr@arm.com>
 
        Revert r253399:

diff --git a/gcc/config/s390/vx-builtins.md b/gcc/config/s390/vx-builtins.md
index 7fb176c2fa47667e0b2c71b27b0a2d1faee906d9..114935550c32c2e4b9ff81bad93bec10852ad0db 100644 (file)
--- a/gcc/config/s390/vx-builtins.md
+++ b/gcc/config/s390/vx-builtins.md
@@ -211,9 +211,9 @@
 ; (vec_select op0) (vec_select op1)
 ; vmrhb, vmrhh, vmrhf, vmrhg
 (define_insn "vec_mergeh<mode>"
-  [(set (match_operand:VEC_HW                 0 "register_operand" "=v")
-       (unspec:VEC_HW [(match_operand:VEC_HW 1 "register_operand"  "v")
-                       (match_operand:VEC_HW 2 "register_operand"  "v")]
+  [(set (match_operand:V_128_NOSINGLE                         0 "register_operand" "=v")
+       (unspec:V_128_NOSINGLE [(match_operand:V_128_NOSINGLE 1 "register_operand"  "v")
+                       (match_operand:V_128_NOSINGLE         2 "register_operand"  "v")]
                       UNSPEC_VEC_MERGEH))]
   "TARGET_VX"
   "vmrh<bhfgq>\t%v0,%1,%2"
@@ -221,9 +221,9 @@
 
 ; vmrlb, vmrlh, vmrlf, vmrlg
 (define_insn "vec_mergel<mode>"
-  [(set (match_operand:VEC_HW                 0 "register_operand" "=v")
-       (unspec:VEC_HW [(match_operand:VEC_HW 1 "register_operand"  "v")
-                       (match_operand:VEC_HW 2 "register_operand"  "v")]
+  [(set (match_operand:V_128_NOSINGLE                         0 "register_operand" "=v")
+       (unspec:V_128_NOSINGLE [(match_operand:V_128_NOSINGLE 1 "register_operand"  "v")
+                       (match_operand:V_128_NOSINGLE         2 "register_operand"  "v")]
                     UNSPEC_VEC_MERGEL))]
   "TARGET_VX"
   "vmrl<bhfgq>\t%v0,%1,%2"