/*
* Initialize gpiolib for GPIOs 0-71.
*/
- orion_gpio_init(NULL, 0, 32, DOVE_GPIO_LO_VIRT_BASE, 0,
+ orion_gpio_init(0, 32, DOVE_GPIO_LO_VIRT_BASE, 0,
IRQ_DOVE_GPIO_START, gpio0_irqs);
- orion_gpio_init(NULL, 32, 32, DOVE_GPIO_HI_VIRT_BASE, 0,
+ orion_gpio_init(32, 32, DOVE_GPIO_HI_VIRT_BASE, 0,
IRQ_DOVE_GPIO_START + 32, gpio1_irqs);
- orion_gpio_init(NULL, 64, 8, DOVE_GPIO2_VIRT_BASE, 0,
+ orion_gpio_init(64, 8, DOVE_GPIO2_VIRT_BASE, 0,
IRQ_DOVE_GPIO_START + 64, gpio2_irqs);
}
* registers for core #1 are at an offset of 0x18 from those of
* core #0.)
*/
- orion_gpio_init(NULL, 0, 32, GPIO_VIRT_BASE,
- mv78xx0_core_index() ? 0x18 : 0,
+ orion_gpio_init(0, 32, GPIO_VIRT_BASE, mv78xx0_core_index() ? 0x18 : 0,
IRQ_MV78XX0_GPIO_START, gpio0_irqs);
}
/*
* Initialize gpiolib for GPIOs 0-31.
*/
- orion_gpio_init(NULL, 0, 32, GPIO_VIRT_BASE, 0,
+ orion_gpio_init(0, 32, GPIO_VIRT_BASE, 0,
IRQ_ORION5X_GPIO_START, gpio0_irqs);
}
irq_gc_unlock(gc);
}
-void __init orion_gpio_init(struct device_node *np,
- int gpio_base, int ngpio,
+void __init orion_gpio_init(int gpio_base, int ngpio,
void __iomem *base, int mask_offset,
int secondary_irq_base,
int irqs[4])
ochip->chip.base = gpio_base;
ochip->chip.ngpio = ngpio;
ochip->chip.can_sleep = 0;
-#ifdef CONFIG_OF
- ochip->chip.of_node = np;
-#endif
ochip->chip.dbg_show = orion_gpio_dbg_show;
spin_lock_init(&ochip->lock);
IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE);
/* Setup irq domain on top of the generic chip. */
- ochip->domain = irq_domain_add_legacy(np,
+ ochip->domain = irq_domain_add_legacy(NULL,
ochip->chip.ngpio,
ochip->secondary_irq_base,
ochip->secondary_irq_base,
void orion_gpio_set_valid(unsigned pin, int mode);
/* Initialize gpiolib. */
-void __init orion_gpio_init(struct device_node *np,
- int gpio_base, int ngpio,
+void __init orion_gpio_init(int gpio_base, int ngpio,
void __iomem *base, int mask_offset,
int secondary_irq_base,
int irq[4]);