wifi: rtw89: 8922ae: disable PCI PHY EQ to improve compatibility

For adaption EQ circuit, this HW design and affected by EIEOS (Electrical
Idle Exit Order Set) amplitude from platform and process from IC, so
disable EQ to improve that.

Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Link: https://patch.msgid.link/20240925013901.9835-3-pkshih@realtek.com

diff --git a/drivers/net/wireless/realtek/rtw89/pci.c b/drivers/net/wireless/realtek/rtw89/pci.c
index 5733192cf3803f55cdffe7e2961f2fafedac7890..c1e0861b7b3ff319fd37f33b6ef696c7bf0feaaf 100644 (file)
--- a/drivers/net/wireless/realtek/rtw89/pci.c
+++ b/drivers/net/wireless/realtek/rtw89/pci.c
@@ -2358,7 +2358,7 @@ static int rtw89_pci_deglitch_setting(struct rtw89_dev *rtwdev)
        return 0;
 }
 
-static void rtw89_pci_disable_eq(struct rtw89_dev *rtwdev)
+static void rtw89_pci_disable_eq_ax(struct rtw89_dev *rtwdev)
 {
        u16 g1_oobs, g2_oobs;
        u32 backup_aspm;
@@ -4254,6 +4254,8 @@ const struct rtw89_pci_gen_def rtw89_pci_gen_ax = {
        .aspm_set = rtw89_pci_aspm_set_ax,
        .clkreq_set = rtw89_pci_clkreq_set_ax,
        .l1ss_set = rtw89_pci_l1ss_set_ax,
+
+       .disable_eq = rtw89_pci_disable_eq_ax,
 };
 EXPORT_SYMBOL(rtw89_pci_gen_ax);
 

diff --git a/drivers/net/wireless/realtek/rtw89/pci.h b/drivers/net/wireless/realtek/rtw89/pci.h
index f101bd932f628afa1e97102832f7c2cef75cbc42..796f6cd3c96568e1576639689e3fe7cae91ba079 100644 (file)
--- a/drivers/net/wireless/realtek/rtw89/pci.h
+++ b/drivers/net/wireless/realtek/rtw89/pci.h
@@ -18,11 +18,16 @@
 #define BAC_OOBS_SEL                   BIT(4)
 #define RAC_ANA0A                      0x0A
 #define B_BAC_EQ_SEL                   BIT(5)
+#define RAC_ANA0B                      0x0B
+#define MANUAL_LVL_MASK                        GENMASK(8, 5)
 #define RAC_ANA0C                      0x0C
 #define B_PCIE_BIT_PSAVE               BIT(15)
 #define RAC_ANA0D                      0x0D
+#define OFFSET_CAL_MODE                        BIT(13)
 #define BAC_RX_TEST_EN                 BIT(6)
 #define RAC_ANA10                      0x10
+#define ADDR_SEL_MASK                  GENMASK(9, 4)
+#define ADDR_SEL_VAL                   0x3C
 #define ADDR_SEL_PINOUT_DIS_VAL                0x3C4
 #define B_PCIE_BIT_PINOUT_DIS          BIT(3)
 #define RAC_REG_REV2                   0x1B
@@ -38,6 +43,7 @@
 #define RAC_ANA1E_G2_VAL               0x6EEA
 #define RAC_ANA1F                      0x1F
 #define OOBS_LEVEL_MASK                        GENMASK(12, 8)
+#define OFFSET_CAL_MASK                        GENMASK(7, 4)
 #define RAC_ANA24                      0x24
 #define B_AX_DEGLITCH                  GENMASK(11, 8)
 #define RAC_ANA26                      0x26
@@ -134,6 +140,11 @@
 #define REG_FILTER_OUT_MASK GENMASK(6, 2)
 #define RAC_MULT 2
 
+#define R_RAC_DIRECT_OFFSET_BE_LANE0_G1 0x3800
+#define R_RAC_DIRECT_OFFSET_BE_LANE1_G1 0x3880
+#define R_RAC_DIRECT_OFFSET_BE_LANE0_G2 0x3900
+#define R_RAC_DIRECT_OFFSET_BE_LANE1_G2 0x3980
+
 #define RTW89_PCI_WR_RETRY_CNT         20
 
 /* Interrupts */
@@ -299,6 +310,7 @@
 #define B_BE_L1SS_TIMEOUT_CTRL BIT(18)
 #define B_BE_ASPM_CTRL_L1 BIT(17)
 #define B_BE_ASPM_CTRL_L0 BIT(16)
+#define B_BE_RTK_ASPM_CTRL_MASK GENMASK(17, 16)
 #define B_BE_XFER_PENDING_FW BIT(11)
 #define B_BE_XFER_PENDING BIT(10)
 #define B_BE_REQ_EXIT_L1 BIT(9)
@@ -1276,6 +1288,8 @@ struct rtw89_pci_gen_def {
        void (*aspm_set)(struct rtw89_dev *rtwdev, bool enable);
        void (*clkreq_set)(struct rtw89_dev *rtwdev, bool enable);
        void (*l1ss_set)(struct rtw89_dev *rtwdev, bool enable);
+
+       void (*disable_eq)(struct rtw89_dev *rtwdev);
 };
 
 struct rtw89_pci_info {
@@ -1767,4 +1781,13 @@ static inline int rtw89_pci_poll_txdma_ch_idle(struct rtw89_dev *rtwdev)
 
        return gen_def->poll_txdma_ch_idle(rtwdev);
 }
+
+static inline void rtw89_pci_disable_eq(struct rtw89_dev *rtwdev)
+{
+       const struct rtw89_pci_info *info = rtwdev->pci_info;
+       const struct rtw89_pci_gen_def *gen_def = info->gen_def;
+
+       gen_def->disable_eq(rtwdev);
+}
+
 #endif

diff --git a/drivers/net/wireless/realtek/rtw89/pci_be.c b/drivers/net/wireless/realtek/rtw89/pci_be.c
index c1415a7b18fffa9b0a876d09557a8b13b0fe1b44..34154506f5d467f70e674a7ce622fbe7044dde61 100644 (file)
--- a/drivers/net/wireless/realtek/rtw89/pci_be.c
+++ b/drivers/net/wireless/realtek/rtw89/pci_be.c
@@ -550,6 +550,79 @@ static int rtw89_pci_lv1rst_start_dma_be(struct rtw89_dev *rtwdev)
        return 0;
 }
 
+static void rtw89_pci_disable_eq_be(struct rtw89_dev *rtwdev)
+{
+       u32 backup_aspm, phy_offset;
+       u16 oobs_val, offset_cal;
+       u16 g1_oobs, g2_oobs;
+       u8 gen;
+
+       if (rtwdev->chip->chip_id != RTL8922A)
+               return;
+
+       g1_oobs = rtw89_read16_mask(rtwdev, R_RAC_DIRECT_OFFSET_BE_LANE0_G1 +
+                                           RAC_ANA09 * RAC_MULT, BAC_OOBS_SEL);
+       g2_oobs = rtw89_read16_mask(rtwdev, R_RAC_DIRECT_OFFSET_BE_LANE0_G2 +
+                                           RAC_ANA09 * RAC_MULT, BAC_OOBS_SEL);
+       if (g1_oobs && g2_oobs)
+               return;
+
+       backup_aspm = rtw89_read32(rtwdev, R_BE_PCIE_MIX_CFG);
+       rtw89_write32_clr(rtwdev, R_BE_PCIE_MIX_CFG, B_BE_RTK_ASPM_CTRL_MASK);
+
+       /* offset K */
+       for (gen = 1; gen <= 2; gen++) {
+               phy_offset = gen == 1 ? R_RAC_DIRECT_OFFSET_BE_LANE0_G1 :
+                                       R_RAC_DIRECT_OFFSET_BE_LANE0_G2;
+
+               rtw89_write16_clr(rtwdev, phy_offset + RAC_ANA19 * RAC_MULT,
+                                 B_PCIE_BIT_RD_SEL);
+       }
+
+       offset_cal = rtw89_read16_mask(rtwdev, R_RAC_DIRECT_OFFSET_BE_LANE0_G1 +
+                                              RAC_ANA1F * RAC_MULT, OFFSET_CAL_MASK);
+
+       for (gen = 1; gen <= 2; gen++) {
+               phy_offset = gen == 1 ? R_RAC_DIRECT_OFFSET_BE_LANE0_G1 :
+                                       R_RAC_DIRECT_OFFSET_BE_LANE0_G2;
+
+               rtw89_write16_mask(rtwdev, phy_offset + RAC_ANA0B * RAC_MULT,
+                                  MANUAL_LVL_MASK, offset_cal);
+               rtw89_write16_clr(rtwdev, phy_offset + RAC_ANA0D * RAC_MULT,
+                                 OFFSET_CAL_MODE);
+       }
+
+       /* OOBS */
+       for (gen = 1; gen <= 2; gen++) {
+               phy_offset = gen == 1 ? R_RAC_DIRECT_OFFSET_BE_LANE0_G1 :
+                                       R_RAC_DIRECT_OFFSET_BE_LANE0_G2;
+
+               rtw89_write16_set(rtwdev, phy_offset + RAC_ANA0D * RAC_MULT,
+                                 BAC_RX_TEST_EN);
+               rtw89_write16_mask(rtwdev, phy_offset + RAC_ANA10 * RAC_MULT,
+                                  ADDR_SEL_MASK, ADDR_SEL_VAL);
+               rtw89_write16_clr(rtwdev, phy_offset + RAC_ANA10 * RAC_MULT,
+                                 B_PCIE_BIT_PINOUT_DIS);
+               rtw89_write16_set(rtwdev, phy_offset + RAC_ANA19 * RAC_MULT,
+                                 B_PCIE_BIT_RD_SEL);
+       }
+
+       oobs_val = rtw89_read16_mask(rtwdev, R_RAC_DIRECT_OFFSET_BE_LANE0_G1 +
+                                            RAC_ANA1F * RAC_MULT, OOBS_LEVEL_MASK);
+
+       for (gen = 1; gen <= 2; gen++) {
+               phy_offset = gen == 1 ? R_RAC_DIRECT_OFFSET_BE_LANE0_G1 :
+                                       R_RAC_DIRECT_OFFSET_BE_LANE0_G2;
+
+               rtw89_write16_mask(rtwdev, phy_offset + RAC_ANA03 * RAC_MULT,
+                                  OOBS_SEN_MASK, oobs_val);
+               rtw89_write16_set(rtwdev, phy_offset + RAC_ANA09 * RAC_MULT,
+                                 BAC_OOBS_SEL);
+       }
+
+       rtw89_write32(rtwdev, R_BE_PCIE_MIX_CFG, backup_aspm);
+}
+
 static int __maybe_unused rtw89_pci_suspend_be(struct device *dev)
 {
        struct ieee80211_hw *hw = dev_get_drvdata(dev);
@@ -616,5 +689,7 @@ const struct rtw89_pci_gen_def rtw89_pci_gen_be = {
        .aspm_set = rtw89_pci_aspm_set_be,
        .clkreq_set = rtw89_pci_clkreq_set_be,
        .l1ss_set = rtw89_pci_l1ss_set_be,
+
+       .disable_eq = rtw89_pci_disable_eq_be,
 };
 EXPORT_SYMBOL(rtw89_pci_gen_be);