]> git.ipfire.org Git - thirdparty/linux.git/commitdiff
drm/amdgpu: Add gmc interface to request NPS mode
authorLijo Lazar <lijo.lazar@amd.com>
Thu, 19 Sep 2024 13:21:07 +0000 (18:51 +0530)
committerAlex Deucher <alexander.deucher@amd.com>
Mon, 7 Oct 2024 18:32:23 +0000 (14:32 -0400)
Add a common interface in GMC to request NPS mode through PSP. Also add
a variable in hive and gmc control to track the last requested mode.

Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com>
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h

index 47ae371ef4a94238babea7faf2de9a19d7749995..a3652ba473453c0cf3b085051b63b0641d3ad2bd 100644 (file)
@@ -1235,3 +1235,19 @@ err:
 
        return ret;
 }
+
+int amdgpu_gmc_request_memory_partition(struct amdgpu_device *adev,
+                                       int nps_mode)
+{
+       /* Not supported on VF devices and APUs */
+       if (amdgpu_sriov_vf(adev) || (adev->flags & AMD_IS_APU))
+               return -EOPNOTSUPP;
+
+       if (!adev->psp.funcs) {
+               dev_err(adev->dev,
+                       "PSP interface not available for nps mode change request");
+               return -EINVAL;
+       }
+
+       return psp_memory_partition(&adev->psp, nps_mode);
+}
index 1970d18a21380d43940cbd6f82254c35d5a2a36d..910cd227d8c253bc2e71b444c563c0e6952b35f3 100644 (file)
@@ -161,6 +161,9 @@ struct amdgpu_gmc_funcs {
 
        enum amdgpu_memory_partition (*query_mem_partition_mode)(
                struct amdgpu_device *adev);
+       /* Request NPS mode */
+       int (*request_mem_partition_mode)(struct amdgpu_device *adev,
+                                         int nps_mode);
 };
 
 struct amdgpu_xgmi_ras {
@@ -304,6 +307,7 @@ struct amdgpu_gmc {
        struct amdgpu_mem_partition_info *mem_partitions;
        uint8_t num_mem_partitions;
        const struct amdgpu_gmc_funcs   *gmc_funcs;
+       enum amdgpu_memory_partition    requested_nps_mode;
 
        struct amdgpu_xgmi xgmi;
        struct amdgpu_irq_src   ecc_irq;
@@ -454,4 +458,6 @@ int amdgpu_gmc_get_nps_memranges(struct amdgpu_device *adev,
                                 struct amdgpu_mem_partition_info *mem_ranges,
                                 int exp_ranges);
 
+int amdgpu_gmc_request_memory_partition(struct amdgpu_device *adev,
+                                       int nps_mode);
 #endif
index 733e69e90c5a085c341bdcdcbb3768b4308935f5..d53789642fc616dde309eed0affe8dc6f457460f 100644 (file)
@@ -667,6 +667,7 @@ struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev)
        task_barrier_init(&hive->tb);
        hive->pstate = AMDGPU_XGMI_PSTATE_UNKNOWN;
        hive->hi_req_gpu = NULL;
+       atomic_set(&hive->requested_nps_mode, UNKNOWN_MEMORY_PARTITION_MODE);
 
        /*
         * hive pstate on boot is high in vega20 so we have to go to low
index d652727ca5655371cda6cff5dd1cff74df6c2194..67abadb4f298ead8ed93f02e9280228755f7570f 100644 (file)
@@ -46,6 +46,7 @@ struct amdgpu_hive_info {
        atomic_t ras_recovery;
        struct ras_event_manager event_mgr;
        struct work_struct reset_on_init_work;
+       atomic_t requested_nps_mode;
 };
 
 struct amdgpu_pcs_ras_field {