aarch64: Fix condition accepted by mov<ALLI>cc

Reject QI/HImode conditions, which would require extension in
order to compare.  Fixes

z.c:10:1: error: unrecognizable insn:
   10 | }
      | ^
(insn 23 22 24 2 (set (reg:CC 66 cc)
        (compare:CC (reg:HI 128)
            (reg:HI 127))) "z.c":6:6 -1
     (nil))
during RTL pass: vregs

gcc:
	* config/aarch64/aarch64.md (mov<ALLI>cc): Accept MODE_CC
	conditions directly; reject QI/HImode conditions.

gcc/testsuite:
	* gcc.target/aarch64/cmpbr-3.c: New.
	* gcc.target/aarch64/ifcvt_multiple_sets_rewire.c: Simplify
	test for csel by ignoring the actual registers used.

diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 77b4bdcb6348cf1a0f7841c820f771b9a0811504..8e431a10cb1de4fa9eb679ef7cd07b33f3c92b72 100644 (file)
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -4771,15 +4771,21 @@
                           (match_operand:ALLI 3 "register_operand")))]
   ""
   {
-    rtx ccreg;
     enum rtx_code code = GET_CODE (operands[1]);
-
     if (code == UNEQ || code == LTGT)
       FAIL;
 
-    ccreg = aarch64_gen_compare_reg (code, XEXP (operands[1], 0),
-                                    XEXP (operands[1], 1));
-    operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx);
+    rtx ccreg = XEXP (operands[1], 0);
+    enum machine_mode ccmode = GET_MODE (ccreg);
+    if (GET_MODE_CLASS (ccmode) == MODE_CC)
+      gcc_assert (XEXP (operands[1], 1) == const0_rtx);
+    else if (ccmode == QImode || ccmode == HImode)
+      FAIL;
+    else
+      {
+       ccreg = aarch64_gen_compare_reg (code, ccreg, XEXP (operands[1], 1));
+       operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx);
+      }
   }
 )
 

diff --git a/gcc/testsuite/gcc.target/aarch64/cmpbr-3.c b/gcc/testsuite/gcc.target/aarch64/cmpbr-3.c
new file mode 100644 (file)
index 0000000..a4f12de
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/cmpbr-3.c
@@ -0,0 +1,15 @@
+/* { dg-do assemble } */
+/* { dg-options "-O2" } */
+
+#pragma GCC target "+cmpbr"
+
+long aarch64_fallback_frame_state_tpidr2_0;
+unsigned short aarch64_fallback_frame_state_tpidr2_1, aarch64_fallback_frame_state_za_ctx_0;
+void aarch64_fallback_frame_state_za_buffer()
+{
+  long num_slices = aarch64_fallback_frame_state_tpidr2_1;
+  if (aarch64_fallback_frame_state_tpidr2_1 > aarch64_fallback_frame_state_za_ctx_0)
+    num_slices = aarch64_fallback_frame_state_za_ctx_0;
+  __builtin_memcpy((void *)aarch64_fallback_frame_state_tpidr2_0,
+         aarch64_fallback_frame_state_za_buffer, num_slices);
+}

diff --git a/gcc/testsuite/gcc.target/aarch64/ifcvt_multiple_sets_rewire.c b/gcc/testsuite/gcc.target/aarch64/ifcvt_multiple_sets_rewire.c
index 448425fba035dc7b10c248b5cc4f30b63404fe5b..2f28756d9a331038dedd22bf1aaec746bd84a0ac 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/ifcvt_multiple_sets_rewire.c
+++ b/gcc/testsuite/gcc.target/aarch64/ifcvt_multiple_sets_rewire.c
@@ -14,7 +14,5 @@ void cond1(int cond, int x, int y, int z)
   sink2(x, y);
 }
 
-/* { dg-final { scan-assembler-times "csel\tw0, w0, w1" 1 } } */
-/* { dg-final { scan-assembler-times "csel\tw1, w3, w2" 1 } } */
-
+/* { dg-final { scan-assembler-times "csel" 2 } } */
 /* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_convert_multiple_sets" 1 "ce1" } } */