EDAC/i10nm: Switch to new Intel CPU model defines

New CPU #defines encode vendor and family as well as model.

Signed-off-by: Tony Luck <tony.luck@intel.com>
Link: https://lore.kernel.org/r/20240520224620.9480-36-tony.luck@intel.com

diff --git a/drivers/edac/i10nm_base.c b/drivers/edac/i10nm_base.c
index 3fd22a1eb1a965362b3422dfbe81f3af7a7a36ff..24dd896d9a9d58c7caed6649faab4eeb10248f3e 100644 (file)
--- a/drivers/edac/i10nm_base.c
+++ b/drivers/edac/i10nm_base.c
@@ -942,16 +942,16 @@ static struct res_config gnr_cfg = {
 };
 
 static const struct x86_cpu_id i10nm_cpuids[] = {
-       X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(ATOM_TREMONT_D,    X86_STEPPINGS(0x0, 0x3), &i10nm_cfg0),
-       X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(ATOM_TREMONT_D,    X86_STEPPINGS(0x4, 0xf), &i10nm_cfg1),
-       X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(ICELAKE_X,         X86_STEPPINGS(0x0, 0x3), &i10nm_cfg0),
-       X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(ICELAKE_X,         X86_STEPPINGS(0x4, 0xf), &i10nm_cfg1),
-       X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(ICELAKE_D,         X86_STEPPINGS(0x0, 0xf), &i10nm_cfg1),
-       X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(SAPPHIRERAPIDS_X,  X86_STEPPINGS(0x0, 0xf), &spr_cfg),
-       X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(EMERALDRAPIDS_X,   X86_STEPPINGS(0x0, 0xf), &spr_cfg),
-       X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(GRANITERAPIDS_X,   X86_STEPPINGS(0x0, 0xf), &gnr_cfg),
-       X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(ATOM_CRESTMONT_X,  X86_STEPPINGS(0x0, 0xf), &gnr_cfg),
-       X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(ATOM_CRESTMONT,    X86_STEPPINGS(0x0, 0xf), &gnr_cfg),
+       X86_MATCH_VFM_STEPPINGS(INTEL_ATOM_TREMONT_D,   X86_STEPPINGS(0x0, 0x3), &i10nm_cfg0),
+       X86_MATCH_VFM_STEPPINGS(INTEL_ATOM_TREMONT_D,   X86_STEPPINGS(0x4, 0xf), &i10nm_cfg1),
+       X86_MATCH_VFM_STEPPINGS(INTEL_ICELAKE_X,        X86_STEPPINGS(0x0, 0x3), &i10nm_cfg0),
+       X86_MATCH_VFM_STEPPINGS(INTEL_ICELAKE_X,        X86_STEPPINGS(0x4, 0xf), &i10nm_cfg1),
+       X86_MATCH_VFM_STEPPINGS(INTEL_ICELAKE_D,        X86_STEPPINGS(0x0, 0xf), &i10nm_cfg1),
+       X86_MATCH_VFM_STEPPINGS(INTEL_SAPPHIRERAPIDS_X, X86_STEPPINGS(0x0, 0xf), &spr_cfg),
+       X86_MATCH_VFM_STEPPINGS(INTEL_EMERALDRAPIDS_X,  X86_STEPPINGS(0x0, 0xf), &spr_cfg),
+       X86_MATCH_VFM_STEPPINGS(INTEL_GRANITERAPIDS_X,  X86_STEPPINGS(0x0, 0xf), &gnr_cfg),
+       X86_MATCH_VFM_STEPPINGS(INTEL_ATOM_CRESTMONT_X, X86_STEPPINGS(0x0, 0xf), &gnr_cfg),
+       X86_MATCH_VFM_STEPPINGS(INTEL_ATOM_CRESTMONT,   X86_STEPPINGS(0x0, 0xf), &gnr_cfg),
        {}
 };
 MODULE_DEVICE_TABLE(x86cpu, i10nm_cpuids);