+2009-04-27 Ian Lance Taylor <iant@google.com>
+
+ * collect2.c (is_ctor_dtor): Change type of ret field in struct
+ names to symkind.
+ * dce.c (run_fast_df_dce): Change type of old_flags to int.
+ * df-core.c (df_set_flags): Change return type to int. Change
+ type of old_flags to int.
+ (df_clear_flags): Likewise.
+ * df-scan.c (df_def_record_1): Change 0 to VOIDmode.
+ (df_get_conditional_uses): Likewise.
+ * df.h (df_set_flags, df_clear_flags): Update declarations.
+ * dwarf2out.c (struct indirect_string_node): Change type of form
+ field to enum dwarf_form.
+ (AT_string_form): Change return type to enum dwarf_form.
+ * fixed-value.c (fixed_compare): Add cast to enum type.
+ * fwprop.c (update_df): Change 0 to VOIDmode.
+ * gensupport.c: Change 0 to UNKNOWN.
+ * gimple.h (gimple_cond_code): Add cast to enum type.
+ * haifa-sched.c (reemit_notes): Add cast to enum type.
+ * hooks.c (hook_int_void_no_regs): Remove function.
+ * hooks.h (hook_int_void_no_regs): Remove declaration.
+ * optabs.c (expand_widen_pattern_expr): Change 0 to VOIDmode.
+ * predict.c (combine_predictions_for_insn): Add casts to enum
+ type.
+ * real.c (real_arithmetic): Add cast to enum type.
+ (real_compare): Likewise.
+ * target.h (struct gcc_target): Change return type of
+ branch_target_register_class to enum reg_class.
+ * target-def.h (TARGET_BRANCH_TARGET_REGISTER_CLASS): Define as
+ default_branch_target_register_class.
+ * targhooks.c (default_branch_target_register_class): New
+ function.
+ * targhooks.h (default_branch_target_register_class): Declare.
+ * tree-data-ref.c (print_direction_vector): Add cast to enum
+ type.
+ * tree-vect-data-refs.c (vect_supportable_dr_alignment): Remove
+ cast to int.
+ * tree-vect-loop.c (vect_create_epilog_for_reduction): Change 0 to
+ ERROR_MARK.
+ * tree-vect-slp.c (vect_build_slp_tree): Change 0 to
+ vect_uninitialized_def. Change 0 to ERROR_MARK.
+ * tree-vect-stmts.c (supportable_widening_operation): Don't
+ initialize icode1 and icode2.
+ * tree-vectorizer.h (enum vect_def_type): Add
+ vect_uninitialized_def.
+ * config/sol2-c.c (cmn_err_length_specs): Change 0 to FMT_LEN_none
+ and to STD_C89.
+ (cmn_err_flag_specs): Change 0 to STD_C89.
+ (cmn_err_char_table): Likewise.
+ * config/arm/arm.c (get_arm_condition_code): Change type of code
+ to enum arm_cond_code.
+ (IWMMXT_BUILTIN): Change 0 to UNKNOWN.
+ (IWMMXT_BUILTIN2): Likewise.
+ (neon_builtin_type_bits): Don't define typedef.
+ (neon_builtin_datum): Change type of bits field to int.
+ (arm_expand_neon_args): Add cast to enum type.
+ * config/ia64/ia64.c (tls_symbolic_operand_type): Change 0 to
+ TLS_MODEL_NONE.
+ * config/i386/i386.c (bdesc_multi_arg): Change 0 to UNKNOWN. Add
+ casts to enum type.
+ * config/mips/mips.c (LOONGSON_BUILTIN_ALIAS): Change 0 to
+ MIPS_FP_COND_f.
+ * config/mips/mips.md (jal_macro): Return enum constant.
+ (single_insn): Likewise.
+ * config/rs6000/rs6000.c (bdesc_altivec_preds): Change 0 to
+ CODE_FOR_nothing.
+ * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add
+ casts to enum type.
+ * config/s390/s390.c (s390_tune_flags): Change type to int.
+ (s390_arch_flags): Likewise.
+ (s390_handle_arch_option): Change flags field of struct pta to
+ int.
+ * config/s390/s390.h (s390_tune_flags): Update declaration.
+ (s390_arch_flags): Likewise.
+ * config/sh/sh.c (prepare_move_operands): Compare
+ tls_symbolic_operand result with enum constant.
+ (sh_reorg): Change PUT_MODE to PUT_REG_NOTE_KIND.
+ (sh_expand_prologue): Add cast to enum type.
+ (sh_expand_epilogue): Likewise.
+ (tls_symbolic_operand): Change return type to enum tls_model.
+ (fpscr_set_from_mem): Add cast to enum type.
+ (legitimize_pic_address): Compare tls_symbolic_operand result with
+ enum constant.
+ (sh_target_reg_class): Change return type to enum reg_class.
+ * config/sh/sh.h (OVERRIDE_OPTIONS): Change CPU_xxx to
+ PROCESSOR_xxx.
+ * config/sh/sh-protos.h (tls_symbolic_operand): Update
+ declaration.
+ * config/sparc/sparc.c (sparc_override_options): Add cast to enum
+ type.
+ * config/sparc/sparc.md (empty_delay_slot): Return enum constant.
+ (pic, calls_alloca, calls_eh_return, leaf_function): Likewise.
+ (delayed_branch, tls_call_delay): Likewise.
+ (eligible_for_sibcall_delay): Likewise.
+ (eligible_for_return_delay): Likewise.
+ * config/spu/spu.c (expand_builtin_args): Add cast to enum type.
+ (spu_expand_builtin_1): Likewise.
+
+ * c-typeck.c (convert_for_assignment): Issue -Wc++-compat warnings
+ for all types of conversions.
+ (output_init_element): Issue -Wc++-compat warning if needed when
+ initializing a bitfield with enum type.
+ * c-parser.c (c_parser_expression): Set original_type to
+ original_type of right hand operand of comman operator.
+
2009-04-27 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
* doc/c-tree.texi (Types, Functions, Expression trees): Fix
next = default_function_array_conversion (next);
expr.value = build_compound_expr (expr.value, next.value);
expr.original_code = COMPOUND_EXPR;
- expr.original_type = NULL;
+ expr.original_type = next.original_type;
}
return expr;
}
&& TREE_CODE (type) == ENUMERAL_TYPE
&& TYPE_MAIN_VARIANT (checktype) != TYPE_MAIN_VARIANT (type))
{
- /* FIXME: Until the gcc source code is converted, we only
- warn about assignment and parameter passing. We will add
- the other cases when bootstrap succeeds with them. */
- if (errtype == ic_argpass || errtype == ic_assign)
- {
- WARN_FOR_ASSIGNMENT (input_location, OPT_Wc___compat,
- G_("enum conversion when passing argument "
- "%d of %qE is invalid in C++"),
- G_("enum conversion in assignment is "
- "invalid in C++"),
- G_("enum conversion in initialization is "
- "invalid in C++"),
- G_("enum conversion in return is "
- "invalid in C++"));
- }
+ WARN_FOR_ASSIGNMENT (input_location, OPT_Wc___compat,
+ G_("enum conversion when passing argument "
+ "%d of %qE is invalid in C++"),
+ G_("enum conversion in assignment is "
+ "invalid in C++"),
+ G_("enum conversion in initialization is "
+ "invalid in C++"),
+ G_("enum conversion in return is "
+ "invalid in C++"));
}
}
pedwarn_init (input_location, 0,
"initializer element is not a constant expression");
+ /* Issue -Wc++-compat warnings about initializing a bitfield with
+ enum type. */
+ if (warn_cxx_compat
+ && field != NULL_TREE
+ && TREE_CODE (field) == FIELD_DECL
+ && DECL_BIT_FIELD_TYPE (field) != NULL_TREE
+ && (TYPE_MAIN_VARIANT (DECL_BIT_FIELD_TYPE (field))
+ != TYPE_MAIN_VARIANT (type))
+ && TREE_CODE (DECL_BIT_FIELD_TYPE (field)) == ENUMERAL_TYPE)
+ {
+ tree checktype = origtype != NULL_TREE ? origtype : TREE_TYPE (value);
+ if (checktype != error_mark_node
+ && (TYPE_MAIN_VARIANT (checktype)
+ != TYPE_MAIN_VARIANT (DECL_BIT_FIELD_TYPE (field))))
+ warning_init (OPT_Wc___compat,
+ "enum conversion in initialization is invalid in C++");
+ }
+
/* If this field is empty (and not at the end of structure),
don't do anything other than checking the initializer. */
if (field
/* Collect static initialization info into data structures that can be
traversed by C++ initialization and finalization routines.
Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998,
- 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2008
+ 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009
Free Software Foundation, Inc.
Contributed by Chris Smith (csmith@convex.com).
Heavily modified by Michael Meissner (meissner@cygnus.com),
static symkind
is_ctor_dtor (const char *s)
{
- struct names { const char *const name; const int len; const int ret;
+ struct names { const char *const name; const int len; symkind ret;
const int two_underscores; };
const struct names *p;
get_arm_condition_code (rtx comparison)
{
enum machine_mode mode = GET_MODE (XEXP (comparison, 0));
- int code;
+ enum arm_cond_code code;
enum rtx_code comp_code = GET_CODE (comparison);
if (GET_MODE_CLASS (mode) != MODE_CC)
{
#define IWMMXT_BUILTIN(code, string, builtin) \
{ FL_IWMMXT, CODE_FOR_##code, "__builtin_arm_" string, \
- ARM_BUILTIN_##builtin, 0, 0 },
+ ARM_BUILTIN_##builtin, UNKNOWN, 0 },
IWMMXT_BUILTIN (addv8qi3, "waddb", WADDB)
IWMMXT_BUILTIN (addv4hi3, "waddh", WADDH)
IWMMXT_BUILTIN (iwmmxt_wmaddu, "wmaddu", WMADDU)
#define IWMMXT_BUILTIN2(code, builtin) \
- { FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, 0, 0 },
+ { FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, UNKNOWN, 0 },
IWMMXT_BUILTIN2 (iwmmxt_wpackhss, WPACKHSS)
IWMMXT_BUILTIN2 (iwmmxt_wpackwss, WPACKWSS)
TREE_READONLY (decl) = 1;
}
-typedef enum {
+enum neon_builtin_type_bits {
T_V8QI = 0x0001,
T_V4HI = 0x0002,
T_V2SI = 0x0004,
T_TI = 0x0400,
T_EI = 0x0800,
T_OI = 0x1000
-} neon_builtin_type_bits;
+};
#define v8qi_UP T_V8QI
#define v4hi_UP T_V4HI
typedef struct {
const char *name;
const neon_itype itype;
- const neon_builtin_type_bits bits;
+ const int bits;
const enum insn_code codes[T_MAX];
const unsigned int num_vars;
unsigned int base_fcode;
for (;;)
{
- builtin_arg thisarg = va_arg (ap, int);
+ builtin_arg thisarg = (builtin_arg) va_arg (ap, int);
if (thisarg == NEON_ARG_STOP)
break;
static const struct builtin_description bdesc_multi_arg[] =
{
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmaddv4sf4, "__builtin_ia32_fmaddss", IX86_BUILTIN_FMADDSS, 0, (int)MULTI_ARG_3_SF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmaddv2df4, "__builtin_ia32_fmaddsd", IX86_BUILTIN_FMADDSD, 0, (int)MULTI_ARG_3_DF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmaddv4sf4, "__builtin_ia32_fmaddps", IX86_BUILTIN_FMADDPS, 0, (int)MULTI_ARG_3_SF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmaddv2df4, "__builtin_ia32_fmaddpd", IX86_BUILTIN_FMADDPD, 0, (int)MULTI_ARG_3_DF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmsubv4sf4, "__builtin_ia32_fmsubss", IX86_BUILTIN_FMSUBSS, 0, (int)MULTI_ARG_3_SF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmsubv2df4, "__builtin_ia32_fmsubsd", IX86_BUILTIN_FMSUBSD, 0, (int)MULTI_ARG_3_DF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmsubv4sf4, "__builtin_ia32_fmsubps", IX86_BUILTIN_FMSUBPS, 0, (int)MULTI_ARG_3_SF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmsubv2df4, "__builtin_ia32_fmsubpd", IX86_BUILTIN_FMSUBPD, 0, (int)MULTI_ARG_3_DF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmaddv4sf4, "__builtin_ia32_fnmaddss", IX86_BUILTIN_FNMADDSS, 0, (int)MULTI_ARG_3_SF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmaddv2df4, "__builtin_ia32_fnmaddsd", IX86_BUILTIN_FNMADDSD, 0, (int)MULTI_ARG_3_DF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmaddv4sf4, "__builtin_ia32_fnmaddps", IX86_BUILTIN_FNMADDPS, 0, (int)MULTI_ARG_3_SF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmaddv2df4, "__builtin_ia32_fnmaddpd", IX86_BUILTIN_FNMADDPD, 0, (int)MULTI_ARG_3_DF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmsubv4sf4, "__builtin_ia32_fnmsubss", IX86_BUILTIN_FNMSUBSS, 0, (int)MULTI_ARG_3_SF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmsubv2df4, "__builtin_ia32_fnmsubsd", IX86_BUILTIN_FNMSUBSD, 0, (int)MULTI_ARG_3_DF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmsubv4sf4, "__builtin_ia32_fnmsubps", IX86_BUILTIN_FNMSUBPS, 0, (int)MULTI_ARG_3_SF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmsubv2df4, "__builtin_ia32_fnmsubpd", IX86_BUILTIN_FNMSUBPD, 0, (int)MULTI_ARG_3_DF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2di, "__builtin_ia32_pcmov", IX86_BUILTIN_PCMOV, 0, (int)MULTI_ARG_3_DI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2di, "__builtin_ia32_pcmov_v2di", IX86_BUILTIN_PCMOV_V2DI, 0, (int)MULTI_ARG_3_DI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v4si, "__builtin_ia32_pcmov_v4si", IX86_BUILTIN_PCMOV_V4SI, 0, (int)MULTI_ARG_3_SI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v8hi, "__builtin_ia32_pcmov_v8hi", IX86_BUILTIN_PCMOV_V8HI, 0, (int)MULTI_ARG_3_HI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v16qi, "__builtin_ia32_pcmov_v16qi",IX86_BUILTIN_PCMOV_V16QI,0, (int)MULTI_ARG_3_QI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2df, "__builtin_ia32_pcmov_v2df", IX86_BUILTIN_PCMOV_V2DF, 0, (int)MULTI_ARG_3_DF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v4sf, "__builtin_ia32_pcmov_v4sf", IX86_BUILTIN_PCMOV_V4SF, 0, (int)MULTI_ARG_3_SF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pperm, "__builtin_ia32_pperm", IX86_BUILTIN_PPERM, 0, (int)MULTI_ARG_3_QI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_permv4sf, "__builtin_ia32_permps", IX86_BUILTIN_PERMPS, 0, (int)MULTI_ARG_3_PERMPS },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_permv2df, "__builtin_ia32_permpd", IX86_BUILTIN_PERMPD, 0, (int)MULTI_ARG_3_PERMPD },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssww, "__builtin_ia32_pmacssww", IX86_BUILTIN_PMACSSWW, 0, (int)MULTI_ARG_3_HI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsww, "__builtin_ia32_pmacsww", IX86_BUILTIN_PMACSWW, 0, (int)MULTI_ARG_3_HI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsswd, "__builtin_ia32_pmacsswd", IX86_BUILTIN_PMACSSWD, 0, (int)MULTI_ARG_3_HI_SI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacswd, "__builtin_ia32_pmacswd", IX86_BUILTIN_PMACSWD, 0, (int)MULTI_ARG_3_HI_SI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdd, "__builtin_ia32_pmacssdd", IX86_BUILTIN_PMACSSDD, 0, (int)MULTI_ARG_3_SI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdd, "__builtin_ia32_pmacsdd", IX86_BUILTIN_PMACSDD, 0, (int)MULTI_ARG_3_SI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdql, "__builtin_ia32_pmacssdql", IX86_BUILTIN_PMACSSDQL, 0, (int)MULTI_ARG_3_SI_DI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdqh, "__builtin_ia32_pmacssdqh", IX86_BUILTIN_PMACSSDQH, 0, (int)MULTI_ARG_3_SI_DI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdql, "__builtin_ia32_pmacsdql", IX86_BUILTIN_PMACSDQL, 0, (int)MULTI_ARG_3_SI_DI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdqh, "__builtin_ia32_pmacsdqh", IX86_BUILTIN_PMACSDQH, 0, (int)MULTI_ARG_3_SI_DI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmadcsswd, "__builtin_ia32_pmadcsswd", IX86_BUILTIN_PMADCSSWD, 0, (int)MULTI_ARG_3_HI_SI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmadcswd, "__builtin_ia32_pmadcswd", IX86_BUILTIN_PMADCSWD, 0, (int)MULTI_ARG_3_HI_SI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv2di3, "__builtin_ia32_protq", IX86_BUILTIN_PROTQ, 0, (int)MULTI_ARG_2_DI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv4si3, "__builtin_ia32_protd", IX86_BUILTIN_PROTD, 0, (int)MULTI_ARG_2_SI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv8hi3, "__builtin_ia32_protw", IX86_BUILTIN_PROTW, 0, (int)MULTI_ARG_2_HI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv16qi3, "__builtin_ia32_protb", IX86_BUILTIN_PROTB, 0, (int)MULTI_ARG_2_QI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv2di3, "__builtin_ia32_protqi", IX86_BUILTIN_PROTQ_IMM, 0, (int)MULTI_ARG_2_DI_IMM },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv4si3, "__builtin_ia32_protdi", IX86_BUILTIN_PROTD_IMM, 0, (int)MULTI_ARG_2_SI_IMM },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv8hi3, "__builtin_ia32_protwi", IX86_BUILTIN_PROTW_IMM, 0, (int)MULTI_ARG_2_HI_IMM },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv16qi3, "__builtin_ia32_protbi", IX86_BUILTIN_PROTB_IMM, 0, (int)MULTI_ARG_2_QI_IMM },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv2di3, "__builtin_ia32_pshaq", IX86_BUILTIN_PSHAQ, 0, (int)MULTI_ARG_2_DI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv4si3, "__builtin_ia32_pshad", IX86_BUILTIN_PSHAD, 0, (int)MULTI_ARG_2_SI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv8hi3, "__builtin_ia32_pshaw", IX86_BUILTIN_PSHAW, 0, (int)MULTI_ARG_2_HI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv16qi3, "__builtin_ia32_pshab", IX86_BUILTIN_PSHAB, 0, (int)MULTI_ARG_2_QI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv2di3, "__builtin_ia32_pshlq", IX86_BUILTIN_PSHLQ, 0, (int)MULTI_ARG_2_DI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv4si3, "__builtin_ia32_pshld", IX86_BUILTIN_PSHLD, 0, (int)MULTI_ARG_2_SI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv8hi3, "__builtin_ia32_pshlw", IX86_BUILTIN_PSHLW, 0, (int)MULTI_ARG_2_HI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv16qi3, "__builtin_ia32_pshlb", IX86_BUILTIN_PSHLB, 0, (int)MULTI_ARG_2_QI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmfrczv4sf2, "__builtin_ia32_frczss", IX86_BUILTIN_FRCZSS, 0, (int)MULTI_ARG_2_SF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmfrczv2df2, "__builtin_ia32_frczsd", IX86_BUILTIN_FRCZSD, 0, (int)MULTI_ARG_2_DF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_frczv4sf2, "__builtin_ia32_frczps", IX86_BUILTIN_FRCZPS, 0, (int)MULTI_ARG_1_SF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_frczv2df2, "__builtin_ia32_frczpd", IX86_BUILTIN_FRCZPD, 0, (int)MULTI_ARG_1_DF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_cvtph2ps, "__builtin_ia32_cvtph2ps", IX86_BUILTIN_CVTPH2PS, 0, (int)MULTI_ARG_1_PH2PS },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_cvtps2ph, "__builtin_ia32_cvtps2ph", IX86_BUILTIN_CVTPS2PH, 0, (int)MULTI_ARG_1_PS2PH },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbw, "__builtin_ia32_phaddbw", IX86_BUILTIN_PHADDBW, 0, (int)MULTI_ARG_1_QI_HI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbd, "__builtin_ia32_phaddbd", IX86_BUILTIN_PHADDBD, 0, (int)MULTI_ARG_1_QI_SI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbq, "__builtin_ia32_phaddbq", IX86_BUILTIN_PHADDBQ, 0, (int)MULTI_ARG_1_QI_DI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddwd, "__builtin_ia32_phaddwd", IX86_BUILTIN_PHADDWD, 0, (int)MULTI_ARG_1_HI_SI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddwq, "__builtin_ia32_phaddwq", IX86_BUILTIN_PHADDWQ, 0, (int)MULTI_ARG_1_HI_DI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadddq, "__builtin_ia32_phadddq", IX86_BUILTIN_PHADDDQ, 0, (int)MULTI_ARG_1_SI_DI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubw, "__builtin_ia32_phaddubw", IX86_BUILTIN_PHADDUBW, 0, (int)MULTI_ARG_1_QI_HI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubd, "__builtin_ia32_phaddubd", IX86_BUILTIN_PHADDUBD, 0, (int)MULTI_ARG_1_QI_SI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubq, "__builtin_ia32_phaddubq", IX86_BUILTIN_PHADDUBQ, 0, (int)MULTI_ARG_1_QI_DI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadduwd, "__builtin_ia32_phadduwd", IX86_BUILTIN_PHADDUWD, 0, (int)MULTI_ARG_1_HI_SI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadduwq, "__builtin_ia32_phadduwq", IX86_BUILTIN_PHADDUWQ, 0, (int)MULTI_ARG_1_HI_DI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddudq, "__builtin_ia32_phaddudq", IX86_BUILTIN_PHADDUDQ, 0, (int)MULTI_ARG_1_SI_DI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubbw, "__builtin_ia32_phsubbw", IX86_BUILTIN_PHSUBBW, 0, (int)MULTI_ARG_1_QI_HI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubwd, "__builtin_ia32_phsubwd", IX86_BUILTIN_PHSUBWD, 0, (int)MULTI_ARG_1_HI_SI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubdq, "__builtin_ia32_phsubdq", IX86_BUILTIN_PHSUBDQ, 0, (int)MULTI_ARG_1_SI_DI },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmaddv4sf4, "__builtin_ia32_fmaddss", IX86_BUILTIN_FMADDSS, UNKNOWN, (int)MULTI_ARG_3_SF },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmaddv2df4, "__builtin_ia32_fmaddsd", IX86_BUILTIN_FMADDSD, UNKNOWN, (int)MULTI_ARG_3_DF },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmaddv4sf4, "__builtin_ia32_fmaddps", IX86_BUILTIN_FMADDPS, UNKNOWN, (int)MULTI_ARG_3_SF },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmaddv2df4, "__builtin_ia32_fmaddpd", IX86_BUILTIN_FMADDPD, UNKNOWN, (int)MULTI_ARG_3_DF },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmsubv4sf4, "__builtin_ia32_fmsubss", IX86_BUILTIN_FMSUBSS, UNKNOWN, (int)MULTI_ARG_3_SF },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmsubv2df4, "__builtin_ia32_fmsubsd", IX86_BUILTIN_FMSUBSD, UNKNOWN, (int)MULTI_ARG_3_DF },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmsubv4sf4, "__builtin_ia32_fmsubps", IX86_BUILTIN_FMSUBPS, UNKNOWN, (int)MULTI_ARG_3_SF },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmsubv2df4, "__builtin_ia32_fmsubpd", IX86_BUILTIN_FMSUBPD, UNKNOWN, (int)MULTI_ARG_3_DF },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmaddv4sf4, "__builtin_ia32_fnmaddss", IX86_BUILTIN_FNMADDSS, UNKNOWN, (int)MULTI_ARG_3_SF },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmaddv2df4, "__builtin_ia32_fnmaddsd", IX86_BUILTIN_FNMADDSD, UNKNOWN, (int)MULTI_ARG_3_DF },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmaddv4sf4, "__builtin_ia32_fnmaddps", IX86_BUILTIN_FNMADDPS, UNKNOWN, (int)MULTI_ARG_3_SF },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmaddv2df4, "__builtin_ia32_fnmaddpd", IX86_BUILTIN_FNMADDPD, UNKNOWN, (int)MULTI_ARG_3_DF },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmsubv4sf4, "__builtin_ia32_fnmsubss", IX86_BUILTIN_FNMSUBSS, UNKNOWN, (int)MULTI_ARG_3_SF },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmsubv2df4, "__builtin_ia32_fnmsubsd", IX86_BUILTIN_FNMSUBSD, UNKNOWN, (int)MULTI_ARG_3_DF },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmsubv4sf4, "__builtin_ia32_fnmsubps", IX86_BUILTIN_FNMSUBPS, UNKNOWN, (int)MULTI_ARG_3_SF },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmsubv2df4, "__builtin_ia32_fnmsubpd", IX86_BUILTIN_FNMSUBPD, UNKNOWN, (int)MULTI_ARG_3_DF },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2di, "__builtin_ia32_pcmov", IX86_BUILTIN_PCMOV, UNKNOWN, (int)MULTI_ARG_3_DI },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2di, "__builtin_ia32_pcmov_v2di", IX86_BUILTIN_PCMOV_V2DI, UNKNOWN, (int)MULTI_ARG_3_DI },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v4si, "__builtin_ia32_pcmov_v4si", IX86_BUILTIN_PCMOV_V4SI, UNKNOWN, (int)MULTI_ARG_3_SI },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v8hi, "__builtin_ia32_pcmov_v8hi", IX86_BUILTIN_PCMOV_V8HI, UNKNOWN, (int)MULTI_ARG_3_HI },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v16qi, "__builtin_ia32_pcmov_v16qi",IX86_BUILTIN_PCMOV_V16QI,UNKNOWN, (int)MULTI_ARG_3_QI },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2df, "__builtin_ia32_pcmov_v2df", IX86_BUILTIN_PCMOV_V2DF, UNKNOWN, (int)MULTI_ARG_3_DF },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v4sf, "__builtin_ia32_pcmov_v4sf", IX86_BUILTIN_PCMOV_V4SF, UNKNOWN, (int)MULTI_ARG_3_SF },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pperm, "__builtin_ia32_pperm", IX86_BUILTIN_PPERM, UNKNOWN, (int)MULTI_ARG_3_QI },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_permv4sf, "__builtin_ia32_permps", IX86_BUILTIN_PERMPS, UNKNOWN, (int)MULTI_ARG_3_PERMPS },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_permv2df, "__builtin_ia32_permpd", IX86_BUILTIN_PERMPD, UNKNOWN, (int)MULTI_ARG_3_PERMPD },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssww, "__builtin_ia32_pmacssww", IX86_BUILTIN_PMACSSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsww, "__builtin_ia32_pmacsww", IX86_BUILTIN_PMACSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsswd, "__builtin_ia32_pmacsswd", IX86_BUILTIN_PMACSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacswd, "__builtin_ia32_pmacswd", IX86_BUILTIN_PMACSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdd, "__builtin_ia32_pmacssdd", IX86_BUILTIN_PMACSSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdd, "__builtin_ia32_pmacsdd", IX86_BUILTIN_PMACSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdql, "__builtin_ia32_pmacssdql", IX86_BUILTIN_PMACSSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdqh, "__builtin_ia32_pmacssdqh", IX86_BUILTIN_PMACSSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdql, "__builtin_ia32_pmacsdql", IX86_BUILTIN_PMACSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdqh, "__builtin_ia32_pmacsdqh", IX86_BUILTIN_PMACSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmadcsswd, "__builtin_ia32_pmadcsswd", IX86_BUILTIN_PMADCSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmadcswd, "__builtin_ia32_pmadcswd", IX86_BUILTIN_PMADCSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv2di3, "__builtin_ia32_protq", IX86_BUILTIN_PROTQ, UNKNOWN, (int)MULTI_ARG_2_DI },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv4si3, "__builtin_ia32_protd", IX86_BUILTIN_PROTD, UNKNOWN, (int)MULTI_ARG_2_SI },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv8hi3, "__builtin_ia32_protw", IX86_BUILTIN_PROTW, UNKNOWN, (int)MULTI_ARG_2_HI },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv16qi3, "__builtin_ia32_protb", IX86_BUILTIN_PROTB, UNKNOWN, (int)MULTI_ARG_2_QI },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv2di3, "__builtin_ia32_protqi", IX86_BUILTIN_PROTQ_IMM, UNKNOWN, (int)MULTI_ARG_2_DI_IMM },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv4si3, "__builtin_ia32_protdi", IX86_BUILTIN_PROTD_IMM, UNKNOWN, (int)MULTI_ARG_2_SI_IMM },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv8hi3, "__builtin_ia32_protwi", IX86_BUILTIN_PROTW_IMM, UNKNOWN, (int)MULTI_ARG_2_HI_IMM },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv16qi3, "__builtin_ia32_protbi", IX86_BUILTIN_PROTB_IMM, UNKNOWN, (int)MULTI_ARG_2_QI_IMM },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv2di3, "__builtin_ia32_pshaq", IX86_BUILTIN_PSHAQ, UNKNOWN, (int)MULTI_ARG_2_DI },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv4si3, "__builtin_ia32_pshad", IX86_BUILTIN_PSHAD, UNKNOWN, (int)MULTI_ARG_2_SI },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv8hi3, "__builtin_ia32_pshaw", IX86_BUILTIN_PSHAW, UNKNOWN, (int)MULTI_ARG_2_HI },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv16qi3, "__builtin_ia32_pshab", IX86_BUILTIN_PSHAB, UNKNOWN, (int)MULTI_ARG_2_QI },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv2di3, "__builtin_ia32_pshlq", IX86_BUILTIN_PSHLQ, UNKNOWN, (int)MULTI_ARG_2_DI },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv4si3, "__builtin_ia32_pshld", IX86_BUILTIN_PSHLD, UNKNOWN, (int)MULTI_ARG_2_SI },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv8hi3, "__builtin_ia32_pshlw", IX86_BUILTIN_PSHLW, UNKNOWN, (int)MULTI_ARG_2_HI },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv16qi3, "__builtin_ia32_pshlb", IX86_BUILTIN_PSHLB, UNKNOWN, (int)MULTI_ARG_2_QI },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmfrczv4sf2, "__builtin_ia32_frczss", IX86_BUILTIN_FRCZSS, UNKNOWN, (int)MULTI_ARG_2_SF },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmfrczv2df2, "__builtin_ia32_frczsd", IX86_BUILTIN_FRCZSD, UNKNOWN, (int)MULTI_ARG_2_DF },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_frczv4sf2, "__builtin_ia32_frczps", IX86_BUILTIN_FRCZPS, UNKNOWN, (int)MULTI_ARG_1_SF },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_frczv2df2, "__builtin_ia32_frczpd", IX86_BUILTIN_FRCZPD, UNKNOWN, (int)MULTI_ARG_1_DF },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_cvtph2ps, "__builtin_ia32_cvtph2ps", IX86_BUILTIN_CVTPH2PS, UNKNOWN, (int)MULTI_ARG_1_PH2PS },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_cvtps2ph, "__builtin_ia32_cvtps2ph", IX86_BUILTIN_CVTPS2PH, UNKNOWN, (int)MULTI_ARG_1_PS2PH },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbw, "__builtin_ia32_phaddbw", IX86_BUILTIN_PHADDBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbd, "__builtin_ia32_phaddbd", IX86_BUILTIN_PHADDBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbq, "__builtin_ia32_phaddbq", IX86_BUILTIN_PHADDBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddwd, "__builtin_ia32_phaddwd", IX86_BUILTIN_PHADDWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddwq, "__builtin_ia32_phaddwq", IX86_BUILTIN_PHADDWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadddq, "__builtin_ia32_phadddq", IX86_BUILTIN_PHADDDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubw, "__builtin_ia32_phaddubw", IX86_BUILTIN_PHADDUBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubd, "__builtin_ia32_phaddubd", IX86_BUILTIN_PHADDUBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubq, "__builtin_ia32_phaddubq", IX86_BUILTIN_PHADDUBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadduwd, "__builtin_ia32_phadduwd", IX86_BUILTIN_PHADDUWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadduwq, "__builtin_ia32_phadduwq", IX86_BUILTIN_PHADDUWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddudq, "__builtin_ia32_phaddudq", IX86_BUILTIN_PHADDUDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubbw, "__builtin_ia32_phsubbw", IX86_BUILTIN_PHSUBBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubwd, "__builtin_ia32_phsubwd", IX86_BUILTIN_PHSUBWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubdq, "__builtin_ia32_phsubdq", IX86_BUILTIN_PHSUBDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
{ OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comeqss", IX86_BUILTIN_COMEQSS, EQ, (int)MULTI_ARG_2_SF_CMP },
{ OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comness", IX86_BUILTIN_COMNESS, NE, (int)MULTI_ARG_2_SF_CMP },
{ OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomgtuq", IX86_BUILTIN_PCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
{ OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomgeuq", IX86_BUILTIN_PCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comfalsess", IX86_BUILTIN_COMFALSESS, COM_FALSE_S, (int)MULTI_ARG_2_SF_TF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comtruess", IX86_BUILTIN_COMTRUESS, COM_TRUE_S, (int)MULTI_ARG_2_SF_TF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comfalseps", IX86_BUILTIN_COMFALSEPS, COM_FALSE_P, (int)MULTI_ARG_2_SF_TF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comtrueps", IX86_BUILTIN_COMTRUEPS, COM_TRUE_P, (int)MULTI_ARG_2_SF_TF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comfalsesd", IX86_BUILTIN_COMFALSESD, COM_FALSE_S, (int)MULTI_ARG_2_DF_TF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comtruesd", IX86_BUILTIN_COMTRUESD, COM_TRUE_S, (int)MULTI_ARG_2_DF_TF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comfalsepd", IX86_BUILTIN_COMFALSEPD, COM_FALSE_P, (int)MULTI_ARG_2_DF_TF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comtruepd", IX86_BUILTIN_COMTRUEPD, COM_TRUE_P, (int)MULTI_ARG_2_DF_TF },
-
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomfalseb", IX86_BUILTIN_PCOMFALSEB, PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomfalsew", IX86_BUILTIN_PCOMFALSEW, PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomfalsed", IX86_BUILTIN_PCOMFALSED, PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomfalseq", IX86_BUILTIN_PCOMFALSEQ, PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomfalseub",IX86_BUILTIN_PCOMFALSEUB,PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomfalseuw",IX86_BUILTIN_PCOMFALSEUW,PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomfalseud",IX86_BUILTIN_PCOMFALSEUD,PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomfalseuq",IX86_BUILTIN_PCOMFALSEUQ,PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
-
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomtrueb", IX86_BUILTIN_PCOMTRUEB, PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomtruew", IX86_BUILTIN_PCOMTRUEW, PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomtrued", IX86_BUILTIN_PCOMTRUED, PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomtrueq", IX86_BUILTIN_PCOMTRUEQ, PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomtrueub", IX86_BUILTIN_PCOMTRUEUB, PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomtrueuw", IX86_BUILTIN_PCOMTRUEUW, PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomtrueud", IX86_BUILTIN_PCOMTRUEUD, PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomtrueuq", IX86_BUILTIN_PCOMTRUEUQ, PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comfalsess", IX86_BUILTIN_COMFALSESS, (enum rtx_code) COM_FALSE_S, (int)MULTI_ARG_2_SF_TF },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comtruess", IX86_BUILTIN_COMTRUESS, (enum rtx_code) COM_TRUE_S, (int)MULTI_ARG_2_SF_TF },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comfalseps", IX86_BUILTIN_COMFALSEPS, (enum rtx_code) COM_FALSE_P, (int)MULTI_ARG_2_SF_TF },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comtrueps", IX86_BUILTIN_COMTRUEPS, (enum rtx_code) COM_TRUE_P, (int)MULTI_ARG_2_SF_TF },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comfalsesd", IX86_BUILTIN_COMFALSESD, (enum rtx_code) COM_FALSE_S, (int)MULTI_ARG_2_DF_TF },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comtruesd", IX86_BUILTIN_COMTRUESD, (enum rtx_code) COM_TRUE_S, (int)MULTI_ARG_2_DF_TF },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comfalsepd", IX86_BUILTIN_COMFALSEPD, (enum rtx_code) COM_FALSE_P, (int)MULTI_ARG_2_DF_TF },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comtruepd", IX86_BUILTIN_COMTRUEPD, (enum rtx_code) COM_TRUE_P, (int)MULTI_ARG_2_DF_TF },
+
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomfalseb", IX86_BUILTIN_PCOMFALSEB, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomfalsew", IX86_BUILTIN_PCOMFALSEW, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomfalsed", IX86_BUILTIN_PCOMFALSED, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomfalseq", IX86_BUILTIN_PCOMFALSEQ, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomfalseub",IX86_BUILTIN_PCOMFALSEUB,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomfalseuw",IX86_BUILTIN_PCOMFALSEUW,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomfalseud",IX86_BUILTIN_PCOMFALSEUD,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomfalseuq",IX86_BUILTIN_PCOMFALSEUQ,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
+
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomtrueb", IX86_BUILTIN_PCOMTRUEB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomtruew", IX86_BUILTIN_PCOMTRUEW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomtrued", IX86_BUILTIN_PCOMTRUED, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomtrueq", IX86_BUILTIN_PCOMTRUEQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomtrueub", IX86_BUILTIN_PCOMTRUEUB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomtrueuw", IX86_BUILTIN_PCOMTRUEUW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomtrueud", IX86_BUILTIN_PCOMTRUEUD, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
+ { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomtrueuq", IX86_BUILTIN_PCOMTRUEUQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
};
/* Set up all the MMX/SSE builtins, even builtins for instructions that are not
static enum tls_model
tls_symbolic_operand_type (rtx addr)
{
- enum tls_model tls_kind = 0;
+ enum tls_model tls_kind = TLS_MODEL_NONE;
if (GET_CODE (addr) == CONST)
{
for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
builtin_description field. */
#define LOONGSON_BUILTIN_ALIAS(INSN, FN_NAME, FUNCTION_TYPE) \
- { CODE_FOR_loongson_ ## INSN, 0, "__builtin_loongson_" #FN_NAME, \
- MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, mips_builtin_avail_loongson }
+ { CODE_FOR_loongson_ ## INSN, MIPS_FP_COND_f, \
+ "__builtin_loongson_" #FN_NAME, MIPS_BUILTIN_DIRECT, \
+ FUNCTION_TYPE, mips_builtin_avail_loongson }
/* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<INSN>
for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
;; the target address into a register.
(define_attr "jal_macro" "no,yes"
(cond [(eq_attr "jal" "direct")
- (symbol_ref "TARGET_CALL_CLOBBERED_GP
- || (flag_pic && !TARGET_ABSOLUTE_ABICALLS)")
+ (symbol_ref "((TARGET_CALL_CLOBBERED_GP
+ || (flag_pic && !TARGET_ABSOLUTE_ABICALLS))
+ ? JAL_MACRO_YES : JAL_MACRO_NO)")
(eq_attr "jal" "indirect")
- (symbol_ref "TARGET_CALL_CLOBBERED_GP")]
+ (symbol_ref "(TARGET_CALL_CLOBBERED_GP
+ ? JAL_MACRO_YES : JAL_MACRO_NO)")]
(const_string "no")))
;; Classification of moves, extensions and truncations. Most values
;; Is it a single instruction?
(define_attr "single_insn" "no,yes"
- (symbol_ref "get_attr_length (insn) == (TARGET_MIPS16 ? 2 : 4)"))
+ (symbol_ref "(get_attr_length (insn) == (TARGET_MIPS16 ? 2 : 4)
+ ? SINGLE_INSN_YES : SINGLE_INSN_NO)"))
;; Can the instruction be put into a delay slot?
(define_attr "can_delay" "no,yes"
{ ALTIVEC_BUILTIN_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGEFP_P,
RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
- { 0, 0, 0, 0, 0, 0 }
+ { (enum rs6000_builtins) 0, (enum rs6000_builtins) 0, 0, 0, 0, 0 }
};
\f
{ MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P },
{ MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P },
- { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpeq_p", ALTIVEC_BUILTIN_VCMPEQ_P },
- { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpgt_p", ALTIVEC_BUILTIN_VCMPGT_P },
- { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpge_p", ALTIVEC_BUILTIN_VCMPGE_P }
+ { MASK_ALTIVEC, CODE_FOR_nothing, NULL, "__builtin_vec_vcmpeq_p", ALTIVEC_BUILTIN_VCMPEQ_P },
+ { MASK_ALTIVEC, CODE_FOR_nothing, NULL, "__builtin_vec_vcmpgt_p", ALTIVEC_BUILTIN_VCMPGT_P },
+ { MASK_ALTIVEC, CODE_FOR_nothing, NULL, "__builtin_vec_vcmpge_p", ALTIVEC_BUILTIN_VCMPGE_P }
};
/* SPE predicates. */
/* Which cpu are we tuning for. */
enum processor_type s390_tune = PROCESSOR_max;
-enum processor_flags s390_tune_flags;
+int s390_tune_flags;
/* Which instruction set architecture to use. */
enum processor_type s390_arch;
-enum processor_flags s390_arch_flags;
+int s390_arch_flags;
HOST_WIDE_INT s390_warn_framesize = 0;
HOST_WIDE_INT s390_stack_size = 0;
static bool
s390_handle_arch_option (const char *arg,
enum processor_type *type,
- enum processor_flags *flags)
+ int *flags)
{
static struct pta
{
const char *const name; /* processor name or nickname. */
const enum processor_type processor;
- const enum processor_flags flags;
+ const int flags; /* From enum processor_flags. */
}
const processor_alias_table[] =
{
/* Definitions of target machine for GNU compiler, for IBM S/390
Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
- 2007, 2008 Free Software Foundation, Inc.
+ 2007, 2008, 2009 Free Software Foundation, Inc.
Contributed by Hartmut Penner (hpenner@de.ibm.com) and
Ulrich Weigand (uweigand@de.ibm.com).
Andreas Krebbel (Andreas.Krebbel@de.ibm.com)
};
extern enum processor_type s390_tune;
-extern enum processor_flags s390_tune_flags;
+extern int s390_tune_flags;
/* This is necessary to avoid a warning about comparing different enum
types. */
#define s390_tune_attr ((enum attr_cpu)s390_tune)
extern enum processor_type s390_arch;
-extern enum processor_flags s390_arch_flags;
+extern int s390_arch_flags;
/* These flags indicate that the generated code should run on a cpu
providing the respective hardware facility regardless of the
extern int get_dest_uid (rtx, int);
extern void final_prescan_insn (rtx, rtx *, int);
extern int symbol_ref_operand (rtx, enum machine_mode);
-extern int tls_symbolic_operand (rtx, enum machine_mode);
+extern enum tls_model tls_symbolic_operand (rtx, enum machine_mode);
extern int system_reg_operand (rtx, enum machine_mode);
extern int general_movsrc_operand (rtx, enum machine_mode);
extern int general_movdst_operand (rtx, enum machine_mode);
static bool sh_function_ok_for_sibcall (tree, tree);
static bool sh_cannot_modify_jumps_p (void);
-static int sh_target_reg_class (void);
+static enum reg_class sh_target_reg_class (void);
static bool sh_optimize_target_register_callee_saved (bool);
static bool sh_ms_bitfield_layout_p (const_tree);
if ((mode == SImode || mode == DImode)
&& flag_pic
&& ! ((mode == Pmode || mode == ptr_mode)
- && tls_symbolic_operand (operands[1], Pmode) != 0))
+ && tls_symbolic_operand (operands[1], Pmode) != TLS_MODEL_NONE))
{
rtx temp;
if (SYMBOLIC_CONST_P (operands[1]))
op1 = operands[1];
if (GET_CODE (op1) == CONST
&& GET_CODE (XEXP (op1, 0)) == PLUS
- && tls_symbolic_operand (XEXP (XEXP (op1, 0), 0), Pmode))
+ && (tls_symbolic_operand (XEXP (XEXP (op1, 0), 0), Pmode)
+ != TLS_MODEL_NONE))
{
opc = XEXP (XEXP (op1, 0), 1);
op1 = XEXP (XEXP (op1, 0), 0);
else
opc = NULL_RTX;
- if ((tls_kind = tls_symbolic_operand (op1, Pmode)))
+ if ((tls_kind = tls_symbolic_operand (op1, Pmode)) != TLS_MODEL_NONE)
{
rtx tga_op1, tga_ret, tmp, tmp2;
/* If we are not optimizing, then there may not be
a note. */
if (note)
- PUT_MODE (note, REG_INC);
+ PUT_REG_NOTE_KIND (note, REG_INC);
*last_float_addr = r0_inc_rtx;
}
tmp_pnt = schedule.temps;
for (entry = &schedule.entries[1]; entry->mode != VOIDmode; entry++)
{
- enum machine_mode mode = entry->mode;
+ enum machine_mode mode = (enum machine_mode) entry->mode;
unsigned int reg = entry->reg;
rtx reg_rtx, mem_rtx, pre_dec = NULL_RTX;
rtx orig_reg_rtx;
tmp_pnt = schedule.temps;
for (; entry->mode != VOIDmode; entry--)
{
- enum machine_mode mode = entry->mode;
+ enum machine_mode mode = (enum machine_mode) entry->mode;
int reg = entry->reg;
rtx reg_rtx, mem_rtx, post_inc = NULL_RTX, insn;
}
/* Return the TLS type for TLS symbols, 0 for otherwise. */
-int
+enum tls_model
tls_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
if (GET_CODE (op) != SYMBOL_REF)
- return 0;
+ return TLS_MODEL_NONE;
return SYMBOL_REF_TLS_MODEL (op);
}
\f
void
fpscr_set_from_mem (int mode, HARD_REG_SET regs_live)
{
- enum attr_fp_mode fp_mode = mode;
+ enum attr_fp_mode fp_mode = (enum attr_fp_mode) mode;
enum attr_fp_mode norm_mode = ACTUAL_NORMAL_MODE (FP_MODE);
rtx addr_reg;
legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED,
rtx reg)
{
- if (tls_symbolic_operand (orig, Pmode))
+ if (tls_symbolic_operand (orig, Pmode) != TLS_MODEL_NONE)
return orig;
if (GET_CODE (orig) == LABEL_REF
return (TARGET_SHMEDIA && (reload_in_progress || reload_completed));
}
-static int
+static enum reg_class
sh_target_reg_class (void)
{
return TARGET_SHMEDIA ? TARGET_REGS : NO_REGS;
/* Definitions of target machine for GNU compiler for Renesas / SuperH SH.
Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
- 2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
+ 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
Contributed by Steve Chamberlain (sac@cygnus.com).
Improved by Jim Wilson (wilson@cygnus.com).
= !flag_signaling_nans && TARGET_SH2E && ! TARGET_IEEE; \
if (TARGET_SH2E && !flag_finite_math_only) \
target_flags |= MASK_IEEE; \
- sh_cpu = CPU_SH1; \
+ sh_cpu = PROCESSOR_SH1; \
assembler_dialect = 0; \
if (TARGET_SH2) \
- sh_cpu = CPU_SH2; \
+ sh_cpu = PROCESSOR_SH2; \
if (TARGET_SH2E) \
- sh_cpu = CPU_SH2E; \
+ sh_cpu = PROCESSOR_SH2E; \
if (TARGET_SH2A) \
{ \
- sh_cpu = CPU_SH2A; \
+ sh_cpu = PROCESSOR_SH2A; \
if (TARGET_SH2A_DOUBLE) \
target_flags |= MASK_FMOVD; \
} \
if (TARGET_SH3) \
- sh_cpu = CPU_SH3; \
+ sh_cpu = PROCESSOR_SH3; \
if (TARGET_SH3E) \
- sh_cpu = CPU_SH3E; \
+ sh_cpu = PROCESSOR_SH3E; \
if (TARGET_SH4) \
{ \
assembler_dialect = 1; \
- sh_cpu = CPU_SH4; \
+ sh_cpu = PROCESSOR_SH4; \
} \
if (TARGET_SH4A_ARCH) \
{ \
assembler_dialect = 1; \
- sh_cpu = CPU_SH4A; \
+ sh_cpu = PROCESSOR_SH4A; \
} \
if (TARGET_SH5) \
{ \
- sh_cpu = CPU_SH5; \
+ sh_cpu = PROCESSOR_SH5; \
target_flags |= MASK_ALIGN_DOUBLE; \
if (TARGET_SHMEDIA_FPU) \
target_flags |= MASK_FMOVD; \
/* Solaris support needed only by C/C++ frontends.
- Copyright (C) 2004, 2005, 2007 Free Software Foundation, Inc.
+ Copyright (C) 2004, 2005, 2007, 2009 Free Software Foundation, Inc.
Contributed by CodeSourcery, LLC.
This file is part of GCC.
static const format_length_info cmn_err_length_specs[] =
{
{ "l", FMT_LEN_l, STD_C89, "ll", FMT_LEN_ll, STD_C89 },
- { NULL, 0, 0, NULL, 0, 0 }
+ { NULL, FMT_LEN_none, STD_C89, NULL, FMT_LEN_none, STD_C89 }
};
static const format_flag_spec cmn_err_flag_specs[] =
{
{ 'w', 0, 0, N_("field width"), N_("field width in printf format"), STD_C89 },
{ 'L', 0, 0, N_("length modifier"), N_("length modifier in printf format"), STD_C89 },
- { 0, 0, 0, NULL, NULL, 0 }
+ { 0, 0, 0, NULL, NULL, STD_C89 }
};
{ "p", 1, STD_C89, { T89_V, BADLEN, BADLEN, BADLEN, BADLEN, BADLEN, BADLEN, BADLEN, BADLEN }, "w", "c", NULL },
{ "s", 1, STD_C89, { T89_C, BADLEN, BADLEN, BADLEN, BADLEN, BADLEN, BADLEN, BADLEN, BADLEN }, "w", "cR", NULL },
{ "b", 0, STD_C89, { T89_I, BADLEN, BADLEN, BADLEN, BADLEN, BADLEN, BADLEN, BADLEN, BADLEN }, "w", "", &bitfield_string_type },
- { NULL, 0, 0, NOLENGTHS, NULL, NULL, NULL }
+ { NULL, 0, STD_C89, NOLENGTHS, NULL, NULL, NULL }
};
const format_kind_info solaris_format_types[] = {
/* UltraSPARC T1 */
{ "niagara", PROCESSOR_NIAGARA, MASK_ISA, MASK_V9|MASK_DEPRECATED_V8_INSNS},
{ "niagara2", PROCESSOR_NIAGARA, MASK_ISA, MASK_V9},
- { 0, 0, 0, 0 }
+ { 0, (enum processor_type) 0, 0, 0 }
};
const struct cpu_table *cpu;
const struct sparc_cpu_select *sel;
;; True if branch/call has empty delay slot and will emit a nop in it
(define_attr "empty_delay_slot" "false,true"
- (symbol_ref "empty_delay_slot (insn)"))
+ (symbol_ref "(empty_delay_slot (insn)
+ ? EMPTY_DELAY_SLOT_TRUE : EMPTY_DELAY_SLOT_FALSE)"))
(define_attr "branch_type" "none,icc,fcc,reg"
(const_string "none"))
(define_attr "pic" "false,true"
- (symbol_ref "flag_pic != 0"))
+ (symbol_ref "(flag_pic != 0 ? PIC_TRUE : PIC_FALSE)"))
(define_attr "calls_alloca" "false,true"
- (symbol_ref "cfun->calls_alloca != 0"))
+ (symbol_ref "(cfun->calls_alloca != 0
+ ? CALLS_ALLOCA_TRUE : CALLS_ALLOCA_FALSE)"))
(define_attr "calls_eh_return" "false,true"
- (symbol_ref "crtl->calls_eh_return !=0 "))
+ (symbol_ref "(crtl->calls_eh_return != 0
+ ? CALLS_EH_RETURN_TRUE : CALLS_EH_RETURN_FALSE)"))
(define_attr "leaf_function" "false,true"
- (symbol_ref "current_function_uses_only_leaf_regs != 0"))
+ (symbol_ref "(current_function_uses_only_leaf_regs != 0
+ ? LEAF_FUNCTION_TRUE : LEAF_FUNCTION_FALSE)"))
(define_attr "delayed_branch" "false,true"
- (symbol_ref "flag_delayed_branch != 0"))
+ (symbol_ref "(flag_delayed_branch != 0
+ ? DELAYED_BRANCH_TRUE : DELAYED_BRANCH_FALSE)"))
;; Length (in # of insns).
;; Beware that setting a length greater or equal to 3 for conditional branches
;; Attributes for instruction and branch scheduling
(define_attr "tls_call_delay" "false,true"
- (symbol_ref "tls_call_delay (insn)"))
+ (symbol_ref "(tls_call_delay (insn)
+ ? TLS_CALL_DELAY_TRUE : TLS_CALL_DELAY_FALSE)"))
(define_attr "in_call_delay" "false,true"
(cond [(eq_attr "type" "uncond_branch,branch,call,sibcall,call_no_delay_slot,multi")
(const_string "false"))))
(define_attr "eligible_for_sibcall_delay" "false,true"
- (symbol_ref "eligible_for_sibcall_delay (insn)"))
+ (symbol_ref "(eligible_for_sibcall_delay (insn)
+ ? ELIGIBLE_FOR_SIBCALL_DELAY_TRUE
+ : ELIGIBLE_FOR_SIBCALL_DELAY_FALSE)"))
(define_attr "eligible_for_return_delay" "false,true"
- (symbol_ref "eligible_for_return_delay (insn)"))
+ (symbol_ref "(eligible_for_return_delay (insn)
+ ? ELIGIBLE_FOR_RETURN_DELAY_TRUE
+ : ELIGIBLE_FOR_RETURN_DELAY_FALSE)"))
;; ??? !v9: Should implement the notion of predelay slots for floating-point
;; branches. This would allow us to remove the nop always inserted before
expand_builtin_args (struct spu_builtin_description *d, tree exp,
rtx target, rtx ops[])
{
- enum insn_code icode = d->icode;
+ enum insn_code icode = (enum insn_code) d->icode;
int i = 0, a;
/* Expand the arguments into rtl. */
{
rtx pat;
rtx ops[8];
- enum insn_code icode = d->icode;
+ enum insn_code icode = (enum insn_code) d->icode;
enum machine_mode mode, tmode;
int i, p;
int n_operands;
+2009-04-27 Ian Lance Taylor <iant@google.com>
+
+ * semantics.c (finish_omp_clauses): Change type of c_kind to enum
+ omp_clause_code.
+
2009-04-27 Jakub Jelinek <jakub@redhat.com>
PR c++/39875
for (pc = &clauses, c = clauses; c ; c = *pc)
{
- enum tree_code c_kind = OMP_CLAUSE_CODE (c);
+ enum omp_clause_code c_kind = OMP_CLAUSE_CODE (c);
bool remove = false;
bool need_complete_non_reference = false;
bool need_default_ctor = false;
/* If dce is able to delete something, it has to happen
immediately. Otherwise there will be problems handling the
eq_notes. */
- enum df_changeable_flags old_flags
- = df_clear_flags (DF_DEFER_INSN_RESCAN + DF_NO_INSN_RESCAN);
-
+ int old_flags =
+ df_clear_flags (DF_DEFER_INSN_RESCAN + DF_NO_INSN_RESCAN);
+
df_in_progress = true;
rest_of_handle_fast_dce ();
df_in_progress = false;
/* Set the MASK flags in the DFLOW problem. The old flags are
returned. If a flag is not allowed to be changed this will fail if
checking is enabled. */
-enum df_changeable_flags
+int
df_set_flags (int changeable_flags)
{
- enum df_changeable_flags old_flags = df->changeable_flags;
+ int old_flags = df->changeable_flags;
df->changeable_flags |= changeable_flags;
return old_flags;
}
/* Clear the MASK flags in the DFLOW problem. The old flags are
returned. If a flag is not allowed to be changed this will fail if
checking is enabled. */
-enum df_changeable_flags
+int
df_clear_flags (int changeable_flags)
{
- enum df_changeable_flags old_flags = df->changeable_flags;
+ int old_flags = df->changeable_flags;
df->changeable_flags &= ~changeable_flags;
return old_flags;
}
rtx dst;
int offset = -1;
int width = -1;
- enum machine_mode mode = 0;
+ enum machine_mode mode = VOIDmode;
enum df_ref_class cl = DF_REF_REGULAR;
/* We may recursively call ourselves on EXPR_LIST when dealing with PARALLEL
{
int width = -1;
int offset = -1;
- enum machine_mode mode = 0;
+ enum machine_mode mode = VOIDmode;
df_ref use;
if (DF_REF_FLAGS_IS_SET (ref, DF_REF_SIGN_EXTRACT | DF_REF_ZERO_EXTRACT))
/* Functions defined in df-core.c. */
extern void df_add_problem (struct df_problem *);
-extern enum df_changeable_flags df_set_flags (int);
-extern enum df_changeable_flags df_clear_flags (int);
+extern int df_set_flags (int);
+extern int df_clear_flags (int);
extern void df_set_blocks (bitmap);
extern void df_remove_problem (struct dataflow *);
extern void df_finish_pass (bool);
struct GTY(()) indirect_string_node {
const char *str;
unsigned int refcount;
- unsigned int form;
+ enum dwarf_form form;
char *label;
};
static int debug_str_eq (const void *, const void *);
static void add_AT_string (dw_die_ref, enum dwarf_attribute, const char *);
static inline const char *AT_string (dw_attr_ref);
-static int AT_string_form (dw_attr_ref);
+static enum dwarf_form AT_string_form (dw_attr_ref);
static void add_AT_die_ref (dw_die_ref, enum dwarf_attribute, dw_die_ref);
static void add_AT_specification (dw_die_ref, dw_die_ref);
static inline dw_die_ref AT_ref (dw_attr_ref);
/* Find out whether a string should be output inline in DIE
or out-of-line in .debug_str section. */
-static int
+static enum dwarf_form
AT_string_form (dw_attr_ref a)
{
struct indirect_string_node *node;
/* Fixed-point arithmetic support.
- Copyright (C) 2006, 2007, 2008 Free Software Foundation, Inc.
+ Copyright (C) 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
This file is part of GCC.
fixed_compare (int icode, const FIXED_VALUE_TYPE *op0,
const FIXED_VALUE_TYPE *op1)
{
- enum tree_code code = icode;
+ enum tree_code code = (enum tree_code) icode;
gcc_assert (op0->mode == op1->mode);
switch (code)
+2009-04-27 Ian Lance Taylor <iant@google.com>
+
+ * trans-intrinsic.c (DEFINE_MATH_BUILTIN): Add casts to enum
+ type.
+ * trans-io.c (st_parameter_field): Add casts to enum type.
+
2009-04-26 Steven G. Kargl <kargl@gcc.gnu.org>
PR fortran/39893
except for atan2. */
#define DEFINE_MATH_BUILTIN(ID, NAME, ARGTYPE) \
{ GFC_ISYM_ ## ID, BUILT_IN_ ## ID ## F, BUILT_IN_ ## ID, \
- BUILT_IN_ ## ID ## L, BUILT_IN_ ## ID ## L, 0, 0, 0, 0, true, \
- false, true, NAME, NULL_TREE, NULL_TREE, NULL_TREE, NULL_TREE, \
- NULL_TREE, NULL_TREE, NULL_TREE, NULL_TREE},
+ BUILT_IN_ ## ID ## L, BUILT_IN_ ## ID ## L, (enum built_in_function) 0, \
+ (enum built_in_function) 0, (enum built_in_function) 0, \
+ (enum built_in_function) 0, true, false, true, NAME, NULL_TREE, \
+ NULL_TREE, NULL_TREE, NULL_TREE, NULL_TREE, NULL_TREE, NULL_TREE, \
+ NULL_TREE},
#define DEFINE_MATH_BUILTIN_C(ID, NAME, ARGTYPE) \
{ GFC_ISYM_ ## ID, BUILT_IN_ ## ID ## F, BUILT_IN_ ## ID, \
{ #name, mask, IOPARM_ptype_##param_type, IOPARM_type_##type, NULL, NULL },
#include "ioparm.def"
#undef IOPARM
- { NULL, 0, 0, 0, NULL, NULL }
+ { NULL, 0, (enum ioparam_type) 0, (enum iofield_type) 0, NULL, NULL }
};
/* Library I/O subroutines */
df_ref orig_use = use, new_use;
int width = -1;
int offset = -1;
- enum machine_mode mode = 0;
+ enum machine_mode mode = VOIDmode;
rtx *new_loc = find_occurrence (loc, DF_REF_REG (orig_use));
use_rec++;
{"register_operand", false, false, {SUBREG, REG}},
{"pmode_register_operand", true, false, {SUBREG, REG}},
{"scratch_operand", false, false, {SCRATCH, REG}},
- {"immediate_operand", false, true, {0}},
+ {"immediate_operand", false, true, {UNKNOWN}},
{"const_int_operand", false, false, {CONST_INT}},
{"const_double_operand", false, false, {CONST_INT, CONST_DOUBLE}},
{"nonimmediate_operand", false, false, {SUBREG, REG, MEM}},
gimple_cond_code (const_gimple gs)
{
GIMPLE_CHECK (gs, GIMPLE_COND);
- return gs->gsbase.subcode;
+ return (enum tree_code) gs->gsbase.subcode;
}
{
if (REG_NOTE_KIND (note) == REG_SAVE_NOTE)
{
- enum insn_note note_type = INTVAL (XEXP (note, 0));
+ enum insn_note note_type = (enum insn_note) INTVAL (XEXP (note, 0));
last = emit_note_before (note_type, last);
remove_note (insn, note);
/* General-purpose hooks.
- Copyright (C) 2002, 2003, 2004, 2005, 2007, 2008
+ Copyright (C) 2002, 2003, 2004, 2005, 2007, 2008, 2009
Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify it
return true;
}
-/* Generic hook that takes no arguments and returns NO_REGS. */
-int
-hook_int_void_no_regs (void)
-{
- return NO_REGS;
-}
-
/* Generic hook that takes (bool) and returns false. */
bool
hook_bool_bool_false (bool a ATTRIBUTE_UNUSED)
/* General-purpose hooks.
- Copyright (C) 2002, 2003, 2004, 2005, 2007, 2008
+ Copyright (C) 2002, 2003, 2004, 2005, 2007, 2008, 2009
Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify it
extern int hook_int_rtx_0 (rtx);
extern int hook_int_rtx_bool_0 (rtx, bool);
extern int hook_int_size_t_constcharptr_int_0 (size_t, const char *, int);
-extern int hook_int_void_no_regs (void);
extern tree hook_tree_tree_tree_null (tree, tree);
extern tree hook_tree_tree_tree_tree_null (tree, tree, tree);
+2009-04-27 Ian Lance Taylor <iant@google.com>
+
+ * builtins.c (java_builtins): Add casts to enum type.
+ * verify-impl.c (check_class_constant): Add cast to enum type.
+ (check_constant, check_wide_constant): Likewise.
+
2009-04-27 Richard Guenther <rguenther@suse.de>
PR java/38374
static GTY(()) struct builtin_record java_builtins[] =
{
- { { "java.lang.Math" }, { "min" }, min_builtin, 0 },
- { { "java.lang.Math" }, { "max" }, max_builtin, 0 },
- { { "java.lang.Math" }, { "abs" }, abs_builtin, 0 },
+ { { "java.lang.Math" }, { "min" }, min_builtin, (enum built_in_function) 0 },
+ { { "java.lang.Math" }, { "max" }, max_builtin, (enum built_in_function) 0 },
+ { { "java.lang.Math" }, { "abs" }, abs_builtin, (enum built_in_function) 0 },
{ { "java.lang.Math" }, { "acos" }, NULL, BUILT_IN_ACOS },
{ { "java.lang.Math" }, { "asin" }, NULL, BUILT_IN_ASIN },
{ { "java.lang.Math" }, { "atan" }, NULL, BUILT_IN_ATAN },
{ { "java.lang.Math" }, { "sin" }, NULL, BUILT_IN_SIN },
{ { "java.lang.Math" }, { "sqrt" }, NULL, BUILT_IN_SQRT },
{ { "java.lang.Math" }, { "tan" }, NULL, BUILT_IN_TAN },
- { { "java.lang.Float" }, { "intBitsToFloat" }, convert_real, 0 },
- { { "java.lang.Double" }, { "longBitsToDouble" }, convert_real, 0 },
- { { "java.lang.Float" }, { "floatToRawIntBits" }, convert_real, 0 },
- { { "java.lang.Double" }, { "doubleToRawLongBits" }, convert_real, 0 },
- { { "sun.misc.Unsafe" }, { "putInt" }, putObject_builtin, 0},
- { { "sun.misc.Unsafe" }, { "putLong" }, putObject_builtin, 0},
- { { "sun.misc.Unsafe" }, { "putObject" }, putObject_builtin, 0},
- { { "sun.misc.Unsafe" }, { "compareAndSwapInt" },
- compareAndSwapInt_builtin, 0},
- { { "sun.misc.Unsafe" }, { "compareAndSwapLong" },
- compareAndSwapLong_builtin, 0},
- { { "sun.misc.Unsafe" }, { "compareAndSwapObject" },
- compareAndSwapObject_builtin, 0},
- { { "sun.misc.Unsafe" }, { "putOrderedInt" }, putVolatile_builtin, 0},
- { { "sun.misc.Unsafe" }, { "putOrderedLong" }, putVolatile_builtin, 0},
- { { "sun.misc.Unsafe" }, { "putOrderedObject" }, putVolatile_builtin, 0},
- { { "sun.misc.Unsafe" }, { "putIntVolatile" }, putVolatile_builtin, 0},
- { { "sun.misc.Unsafe" }, { "putLongVolatile" }, putVolatile_builtin, 0},
- { { "sun.misc.Unsafe" }, { "putObjectVolatile" }, putVolatile_builtin, 0},
- { { "sun.misc.Unsafe" }, { "getObjectVolatile" }, getVolatile_builtin, 0},
- { { "sun.misc.Unsafe" }, { "getIntVolatile" }, getVolatile_builtin, 0},
- { { "sun.misc.Unsafe" }, { "getLongVolatile" }, getVolatile_builtin, 0},
- { { "sun.misc.Unsafe" }, { "getLong" }, getVolatile_builtin, 0},
- { { "java.util.concurrent.atomic.AtomicLong" }, { "VMSupportsCS8" },
- VMSupportsCS8_builtin, 0},
+ { { "java.lang.Float" }, { "intBitsToFloat" }, convert_real,
+ (enum built_in_function) 0 },
+ { { "java.lang.Double" }, { "longBitsToDouble" }, convert_real,
+ (enum built_in_function) 0 },
+ { { "java.lang.Float" }, { "floatToRawIntBits" }, convert_real,
+ (enum built_in_function) 0 },
+ { { "java.lang.Double" }, { "doubleToRawLongBits" }, convert_real,
+ (enum built_in_function) 0 },
+ { { "sun.misc.Unsafe" }, { "putInt" }, putObject_builtin,
+ (enum built_in_function) 0},
+ { { "sun.misc.Unsafe" }, { "putLong" }, putObject_builtin,
+ (enum built_in_function) 0},
+ { { "sun.misc.Unsafe" }, { "putObject" }, putObject_builtin,
+ (enum built_in_function) 0},
+ { { "sun.misc.Unsafe" }, { "compareAndSwapInt" },
+ compareAndSwapInt_builtin, (enum built_in_function) 0},
+ { { "sun.misc.Unsafe" }, { "compareAndSwapLong" },
+ compareAndSwapLong_builtin, (enum built_in_function) 0},
+ { { "sun.misc.Unsafe" }, { "compareAndSwapObject" },
+ compareAndSwapObject_builtin, (enum built_in_function) 0},
+ { { "sun.misc.Unsafe" }, { "putOrderedInt" }, putVolatile_builtin,
+ (enum built_in_function) 0},
+ { { "sun.misc.Unsafe" }, { "putOrderedLong" }, putVolatile_builtin,
+ (enum built_in_function) 0},
+ { { "sun.misc.Unsafe" }, { "putOrderedObject" }, putVolatile_builtin,
+ (enum built_in_function) 0},
+ { { "sun.misc.Unsafe" }, { "putIntVolatile" }, putVolatile_builtin,
+ (enum built_in_function) 0},
+ { { "sun.misc.Unsafe" }, { "putLongVolatile" }, putVolatile_builtin,
+ (enum built_in_function) 0},
+ { { "sun.misc.Unsafe" }, { "putObjectVolatile" }, putVolatile_builtin,
+ (enum built_in_function) 0},
+ { { "sun.misc.Unsafe" }, { "getObjectVolatile" }, getVolatile_builtin,
+ (enum built_in_function) 0},
+ { { "sun.misc.Unsafe" }, { "getIntVolatile" }, getVolatile_builtin,
+ (enum built_in_function) 0},
+ { { "sun.misc.Unsafe" }, { "getLongVolatile" }, getVolatile_builtin, (enum built_in_function) 0},
+ { { "sun.misc.Unsafe" }, { "getLong" }, getVolatile_builtin,
+ (enum built_in_function) 0},
+ { { "java.util.concurrent.atomic.AtomicLong" }, { "VMSupportsCS8" },
+ VMSupportsCS8_builtin, (enum built_in_function) 0},
{ { NULL }, { NULL }, NULL, END_BUILTINS }
};
static type
check_class_constant (int index)
{
- type t = { 0, 0, 0 };
+ type t = { (type_val) 0, 0, 0 };
vfy_constants *pool;
check_pool_index (index);
static type
check_constant (int index)
{
- type t = { 0, 0, 0 };
+ type t = { (type_val) 0, 0, 0 };
vfy_constants *pool;
check_pool_index (index);
static type
check_wide_constant (int index)
{
- type t = { 0, 0, 0 };
+ type t = { (type_val) 0, 0, 0 };
vfy_constants *pool;
check_pool_index (index);
+2009-04-27 Ian Lance Taylor <iant@google.com>
+
+ * objc-act.c (objc_gimplify_expr): Add casts to enum type.
+
2009-04-24 Ian Lance Taylor <iant@google.com>
* objc-act.c (get_super_receiver): Update calls to
}
#ifdef OBJCPLUS
- return cp_gimplify_expr (expr_p, pre_p, post_p);
+ return (enum gimplify_status) cp_gimplify_expr (expr_p, pre_p, post_p);
#else
- return c_gimplify_expr (expr_p, pre_p, post_p);
+ return (enum gimplify_status) c_gimplify_expr (expr_p, pre_p, post_p);
#endif
}
int unsignedp)
{
tree oprnd0, oprnd1, oprnd2;
- enum machine_mode wmode = 0, tmode0, tmode1 = 0;
+ enum machine_mode wmode = VOIDmode, tmode0, tmode1 = VOIDmode;
optab widen_pattern_optab;
int icode;
- enum machine_mode xmode0, xmode1 = 0, wxmode = 0;
+ enum machine_mode xmode0, xmode1 = VOIDmode, wxmode = VOIDmode;
rtx temp;
rtx pat;
rtx xop0, xop1, wxop;
for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
if (REG_NOTE_KIND (note) == REG_BR_PRED)
{
- enum br_predictor predictor = INTVAL (XEXP (XEXP (note, 0), 0));
+ enum br_predictor predictor = ((enum br_predictor)
+ INTVAL (XEXP (XEXP (note, 0), 0)));
int probability = INTVAL (XEXP (XEXP (note, 0), 1));
found = true;
{
if (REG_NOTE_KIND (*pnote) == REG_BR_PRED)
{
- enum br_predictor predictor = INTVAL (XEXP (XEXP (*pnote, 0), 0));
+ enum br_predictor predictor = ((enum br_predictor)
+ INTVAL (XEXP (XEXP (*pnote, 0), 0)));
int probability = INTVAL (XEXP (XEXP (*pnote, 0), 1));
dump_prediction (dump_file, predictor, probability, bb,
real_arithmetic (REAL_VALUE_TYPE *r, int icode, const REAL_VALUE_TYPE *op0,
const REAL_VALUE_TYPE *op1)
{
- enum tree_code code = icode;
+ enum tree_code code = (enum tree_code) icode;
if (op0->decimal || (op1 && op1->decimal))
return decimal_real_arithmetic (r, code, op0, op1);
real_compare (int icode, const REAL_VALUE_TYPE *op0,
const REAL_VALUE_TYPE *op1)
{
- enum tree_code code = icode;
+ enum tree_code code = (enum tree_code) icode;
switch (code)
{
/* In hooks.c. */
#define TARGET_CANNOT_MODIFY_JUMPS_P hook_bool_void_false
-#define TARGET_BRANCH_TARGET_REGISTER_CLASS hook_int_void_no_regs
+#define TARGET_BRANCH_TARGET_REGISTER_CLASS \
+ default_branch_target_register_class
#define TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED hook_bool_bool_false
#define TARGET_CANNOT_FORCE_CONST_MEM hook_bool_rtx_false
#define TARGET_CANNOT_COPY_INSN_P NULL
/* Return a register class for which branch target register
optimizations should be applied. */
- int (* branch_target_register_class) (void);
+ enum reg_class (* branch_target_register_class) (void);
/* Return true if branch target register optimizations should include
callee-saved registers that are not already live during the current
return virtual_incoming_args_rtx;
}
+enum reg_class
+default_branch_target_register_class (void)
+{
+ return NO_REGS;
+}
+
#ifdef IRA_COVER_CLASSES
const enum reg_class *
default_ira_cover_classes (void)
extern bool hook_bool_const_rtx_commutative_p (const_rtx, int);
extern rtx default_function_value (const_tree, const_tree, bool);
extern rtx default_internal_arg_pointer (void);
+extern enum reg_class default_branch_target_register_class (void);
#ifdef IRA_COVER_CLASSES
extern const enum reg_class *default_ira_cover_classes (void);
#endif
+2009-04-27 Ian Lance Taylor <iant@google.com>
+
+ * gcc.dg/Wcxx-compat-5.c: New testcase.
+ * gcc.dg/Wcxx-compat-6.c: New testcase.
+
2009-04-27 Trevor Smigiel <trevor_smigiel@playstation.sony.com>
Allow non-constant arguments to conversion intrinsics.
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-Wc++-compat" } */
+enum E1 { A, B, C };
+enum E2 { D, E, F };
+
+int f1() { return A; }
+
+struct s { enum E1 e1 : 3; enum E2 e2 : 4; };
+
+enum E1
+f2 (int i, struct s sv, struct s *pv)
+{
+ int a;
+ enum E1 e1 = B;
+ enum E2 e2 = E;
+ switch (i)
+ {
+ case 0:
+ return A;
+ case 1:
+ return D; /* { dg-warning "invalid in C\[+\]\[+\]" } */
+ case 2:
+ return 0; /* { dg-warning "invalid in C\[+\]\[+\]" } */
+ case 3:
+ return (enum E1) 1;
+ case 4:
+ return (enum E2) 2; /* { dg-warning "invalid in C\[+\]\[+\]" } */
+ case 5:
+ return e1;
+ case 6:
+ return e2; /* { dg-warning "invalid in C\[+\]\[+\]" } */
+ case 7:
+ return pv->e1;
+ case 8:
+ return sv.e1;
+ case 9:
+ return pv->e2; /* { dg-warning "invalid in C\[+\]\[+\]" } */
+ case 10:
+ return sv.e2; /* { dg-warning "invalid in C\[+\]\[+\]" } */
+ case 11:
+ return 1, A;
+ default:
+ return C;
+ }
+}
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-Wc++-compat" } */
+enum E1 { A, B, C };
+enum E2 { D, E, F };
+
+enum E1 v1a = A;
+enum E1 v1b = D; /* { dg-warning "invalid in C\[+\]\[+\]" } */
+enum E1 v1c = 0; /* { dg-warning "invalid in C\[+\]\[+\]" } */
+enum E1 v1d = (enum E1) 0;
+enum E1 v1e = (enum E2) 0; /* { dg-warning "invalid in C\[+\]\[+\]" } */
+
+enum E2 v2a;
+
+enum E1 a1[] =
+{
+ A,
+ D, /* { dg-warning "invalid in C\[+\]\[+\]" } */
+ 0, /* { dg-warning "invalid in C\[+\]\[+\]" } */
+ (enum E1) 0,
+ (enum E2) 0, /* { dg-warning "invalid in C\[+\]\[+\]" } */
+ A
+};
+
+struct s1
+{
+ enum E1 e1;
+};
+
+struct s1 a2[] =
+{
+ { A },
+ { D }, /* { dg-warning "invalid in C\[+\]\[+\]" } */
+ { 0 }, /* { dg-warning "invalid in C\[+\]\[+\]" } */
+ { (enum E1) 0 },
+ { (enum E2) 0 }, /* { dg-warning "invalid in C\[+\]\[+\]" } */
+ { A }
+};
+
+struct s1 a3[] =
+{
+ [ 5 ] = { .e1 = A },
+ [ 4 ] = { .e1 = D }, /* { dg-warning "invalid in C\[+\]\[+\]" } */
+ [ 3 ] = { .e1 = 0 }, /* { dg-warning "invalid in C\[+\]\[+\]" } */
+ [ 2 ] = { .e1 = (enum E1) 0 },
+ [ 1 ] = { .e1 = (enum E2) 0 }, /* { dg-warning "invalid in C\[+\]\[+\]" } */
+ [ 0 ] = { .e1 = A }
+};
+
+struct s2
+{
+ enum E1 e1 : 3;
+};
+
+struct s2 a4[] =
+{
+ { A },
+ { D }, /* { dg-warning "invalid in C\[+\]\[+\]" } */
+ { 0 }, /* { dg-warning "invalid in C\[+\]\[+\]" } */
+ { (enum E1) 0 },
+ { (enum E2) 0 }, /* { dg-warning "invalid in C\[+\]\[+\]" } */
+ { A }
+};
+
+struct s2 a5[] =
+{
+ [ 5 ] = { .e1 = A },
+ [ 4 ] = { .e1 = D }, /* { dg-warning "invalid in C\[+\]\[+\]" } */
+ [ 3 ] = { .e1 = 0 }, /* { dg-warning "invalid in C\[+\]\[+\]" } */
+ [ 2 ] = { .e1 = (enum E1) 0 },
+ [ 1 ] = { .e1 = (enum E2) 0 }, /* { dg-warning "invalid in C\[+\]\[+\]" } */
+ [ 0 ] = { .e1 = A }
+};
+
+void
+f(enum E1 e1, enum E2 e2, struct s1 vs1, struct s1 *vp1)
+{
+ enum E1 va1[] = {
+ e1,
+ e2, /* { dg-warning "invalid in C\[+\]\[+\]" } */
+ v1a,
+ v2a, /* { dg-warning "invalid in C\[+\]\[+\]" } */
+ vs1.e1,
+ vp1->e1,
+ e1 ? e1 : e1,
+ (0, e1)
+ };
+
+ struct s1 va2[] = {
+ { e1 },
+ { e2 }, /* { dg-warning "invalid in C\[+\]\[+\]" } */
+ { v1a },
+ { v2a }, /* { dg-warning "invalid in C\[+\]\[+\]" } */
+ { vs1.e1 },
+ { vp1->e1 },
+ { e1 ? e1 : e1 },
+ { (0, e1) }
+ };
+
+ struct s2 va3[] = {
+ { e1 },
+ { e2 }, /* { dg-warning "invalid in C\[+\]\[+\]" } */
+ { v1a },
+ { v2a }, /* { dg-warning "invalid in C\[+\]\[+\]" } */
+ { vs1.e1 },
+ { vp1->e1 },
+ { e1 ? e1 : e1 },
+ { (0, e1) }
+ };
+}
+
+/* Match all extra informative notes. */
+/* { dg-warning "near initialization for" "expected" { target *-*-* } 0 } */
for (eq = 0; eq < length; eq++)
{
- enum data_dependence_direction dir = dirv[eq];
+ enum data_dependence_direction dir = ((enum data_dependence_direction)
+ dirv[eq]);
switch (dir)
{
gimple stmt = DR_STMT (dr);
stmt_vec_info stmt_info = vinfo_for_stmt (stmt);
tree vectype = STMT_VINFO_VECTYPE (stmt_info);
- enum machine_mode mode = (int) TYPE_MODE (vectype);
+ enum machine_mode mode = TYPE_MODE (vectype);
struct loop *vect_loop = LOOP_VINFO_LOOP (STMT_VINFO_LOOP_VINFO (stmt_info));
bool nested_in_vect_loop = nested_in_vect_loop_p (vect_loop, stmt);
bool invariant_in_outerloop = false;
}
else
{
- enum tree_code shift_code = 0;
+ enum tree_code shift_code = ERROR_MARK;
bool have_whole_vector_shift = true;
int bit_offset;
int element_bitsize = tree_low_cst (bitsize, 1);
unsigned int i;
VEC (gimple, heap) *stmts = SLP_TREE_SCALAR_STMTS (*node);
gimple stmt = VEC_index (gimple, stmts, 0);
- enum vect_def_type first_stmt_dt0 = 0, first_stmt_dt1 = 0;
- enum tree_code first_stmt_code = 0, rhs_code;
+ enum vect_def_type first_stmt_dt0 = vect_uninitialized_def;
+ enum vect_def_type first_stmt_dt1 = vect_uninitialized_def;
+ enum tree_code first_stmt_code = ERROR_MARK, rhs_code;
tree first_stmt_def1_type = NULL_TREE, first_stmt_def0_type = NULL_TREE;
tree lhs;
bool stop_recursion = false, need_same_oprnds = false;
struct loop *vect_loop = LOOP_VINFO_LOOP (loop_info);
bool ordered_p;
enum machine_mode vec_mode;
- enum insn_code icode1 = 0, icode2 = 0;
+ enum insn_code icode1, icode2;
optab optab1, optab2;
tree type = gimple_expr_type (stmt);
tree wide_vectype = get_vectype_for_scalar_type (type);
/* Define type of def-use cross-iteration cycle. */
enum vect_def_type {
- vect_constant_def = 1,
+ vect_uninitialized_def = 0,
+ vect_constant_def,
vect_invariant_def,
vect_loop_def,
vect_induction_def,
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