ARM: tegra: Fix FLOW_CTLR_HALT register clobbering by tegra_resume()

commit d70f7d31a9e2088e8a507194354d41ea10062994 upstream.

There is an unfortunate typo in the code that results in writing to
FLOW_CTLR_HALT instead of FLOW_CTLR_CSR.

Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Ben Hutchings <ben@decadent.org.uk>

diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S
index 6448324aa9b4b733e90a0d5f1bc18f8fab99780a..f22b131a7c74c7a5366338dbca73655787214d14 100644 (file)
--- a/arch/arm/mach-tegra/reset-handler.S
+++ b/arch/arm/mach-tegra/reset-handler.S
@@ -55,16 +55,16 @@ ENTRY(tegra_resume)
        cmp     r6, #TEGRA20
        beq     1f                              @ Yes
        /* Clear the flow controller flags for this CPU. */
-       cpu_to_csr_reg r1, r0
+       cpu_to_csr_reg r3, r0
        mov32   r2, TEGRA_FLOW_CTRL_BASE
-       ldr     r1, [r2, r1]
+       ldr     r1, [r2, r3]
        /* Clear event & intr flag */
        orr     r1, r1, \
                #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
        movw    r0, #0x3FFD     @ enable, cluster_switch, immed, bitmaps
                                @ & ext flags for CPU power mgnt
        bic     r1, r1, r0
-       str     r1, [r2]
+       str     r1, [r2, r3]
 1:
 
        mov32   r9, 0xc09