mtd: spi-nor: micron-st: Enable locking for mt25qu256a

mt25qu256a [1] uses the 4 bit Block Protection scheme and supports
Top/Bottom protection via the BP and TB bits of the Status Register.
BP3 is located in bit 6 of the Status Register.
Tested on MT25QU256ABA8ESF-0SIT.

[1] https://www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/mt25q/die-rev-a/mt25q_qljs_u_256_aba_0.pdf

Signed-off-by: Eliav Farber <farbere@amazon.com>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Michael Walle <michael@walle.cc>
Link: https://lore.kernel.org/r/20221020092058.33844-1-farbere@amazon.com

diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c
index 3c8a90b39c8c63139ebe220941a00242a65b75cb..7bb86df52f0ba6e41ba8dc6c2351e5897d571dda 100644 (file)
--- a/drivers/mtd/spi-nor/micron-st.c
+++ b/drivers/mtd/spi-nor/micron-st.c
@@ -205,6 +205,8 @@ static const struct flash_info st_nor_parts[] = {
                MFR_FLAGS(USE_FSR)
        },
        { "mt25qu256a",  INFO6(0x20bb19, 0x104400, 64 * 1024,  512)
+               FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
+                     SPI_NOR_BP3_SR_BIT6)
                NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
                FIXUP_FLAGS(SPI_NOR_4B_OPCODES)
                MFR_FLAGS(USE_FSR)