riscv: dts: thead: add ziccrse for th1520

Existing rv64 hardware conforms to the rva20 profile.

Ziccrse is an additional extension required by the rva20 profile, so
th1520 has this extension.

Signed-off-by: Han Gao <rabenda.cn@gmail.com>
Reviewed-by: Drew Fustini <fustini@kernel.org>
Signed-off-by: Drew Fustini <fustini@kernel.org>

diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
index 0b57699ba398d596ffe1feb330ed21589a6e42f4..8e50e24040c2b59a9a2d0a8a4d62a55e622b026c 100644 (file)
--- a/arch/riscv/boot/dts/thead/th1520.dtsi
+++ b/arch/riscv/boot/dts/thead/th1520.dtsi
@@ -24,8 +24,10 @@
                        device_type = "cpu";
                        riscv,isa = "rv64imafdc";
                        riscv,isa-base = "rv64i";
-                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
-                                              "zifencei", "zihpm", "xtheadvector";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+                                              "ziccrse", "zicntr", "zicsr",
+                                              "zifencei", "zihpm",
+                                              "xtheadvector";
                        thead,vlenb = <16>;
                        reg = <0>;
                        i-cache-block-size = <64>;
@@ -49,8 +51,10 @@
                        device_type = "cpu";
                        riscv,isa = "rv64imafdc";
                        riscv,isa-base = "rv64i";
-                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
-                                              "zifencei", "zihpm", "xtheadvector";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+                                              "ziccrse", "zicntr", "zicsr",
+                                              "zifencei", "zihpm",
+                                              "xtheadvector";
                        thead,vlenb = <16>;
                        reg = <1>;
                        i-cache-block-size = <64>;
@@ -74,8 +78,10 @@
                        device_type = "cpu";
                        riscv,isa = "rv64imafdc";
                        riscv,isa-base = "rv64i";
-                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
-                                              "zifencei", "zihpm", "xtheadvector";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+                                              "ziccrse", "zicntr", "zicsr",
+                                              "zifencei", "zihpm",
+                                              "xtheadvector";
                        thead,vlenb = <16>;
                        reg = <2>;
                        i-cache-block-size = <64>;
@@ -99,8 +105,10 @@
                        device_type = "cpu";
                        riscv,isa = "rv64imafdc";
                        riscv,isa-base = "rv64i";
-                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
-                                              "zifencei", "zihpm", "xtheadvector";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+                                              "ziccrse", "zicntr", "zicsr",
+                                              "zifencei", "zihpm",
+                                              "xtheadvector";
                        thead,vlenb = <16>;
                        reg = <3>;
                        i-cache-block-size = <64>;