5.4-stable patches

added patches:
	pci-acpi-add-ampere-altra-soc-mcfg-quirk.patch

diff --git a/queue-5.4/pci-acpi-add-ampere-altra-soc-mcfg-quirk.patch b/queue-5.4/pci-acpi-add-ampere-altra-soc-mcfg-quirk.patch
new file mode 100644 (file)
index 0000000..bcea26d
--- /dev/null
+++ b/queue-5.4/pci-acpi-add-ampere-altra-soc-mcfg-quirk.patch
@@ -0,0 +1,82 @@
+From 877c1a5f79c6984bbe3f2924234c08e2f4f1acd5 Mon Sep 17 00:00:00 2001
+From: Tuan Phan <tuanphan@os.amperecomputing.com>
+Date: Thu, 6 Aug 2020 14:57:34 -0700
+Subject: PCI/ACPI: Add Ampere Altra SOC MCFG quirk
+
+From: Tuan Phan <tuanphan@os.amperecomputing.com>
+
+commit 877c1a5f79c6984bbe3f2924234c08e2f4f1acd5 upstream.
+
+Ampere Altra SOC supports only 32-bit ECAM reads.  Add an MCFG quirk for
+the platform.
+
+Link: https://lore.kernel.org/r/1596751055-12316-1-git-send-email-tuanphan@os.amperecomputing.com
+Signed-off-by: Tuan Phan <tuanphan@os.amperecomputing.com>
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+[ dannf: backport drops const qualifier from pci_32b_read_ops for
+  consistency with the other quirks that weren't yet constified in v5.4 ]
+Signed-off-by: dann frazier <dann.frazier@canonical.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/acpi/pci_mcfg.c  |   20 ++++++++++++++++++++
+ drivers/pci/ecam.c       |   10 ++++++++++
+ include/linux/pci-ecam.h |    1 +
+ 3 files changed, 31 insertions(+)
+
+--- a/drivers/acpi/pci_mcfg.c
++++ b/drivers/acpi/pci_mcfg.c
+@@ -142,6 +142,26 @@ static struct mcfg_fixup mcfg_quirks[] =
+       XGENE_V2_ECAM_MCFG(4, 0),
+       XGENE_V2_ECAM_MCFG(4, 1),
+       XGENE_V2_ECAM_MCFG(4, 2),
++
++#define ALTRA_ECAM_QUIRK(rev, seg) \
++      { "Ampere", "Altra   ", rev, seg, MCFG_BUS_ANY, &pci_32b_read_ops }
++
++      ALTRA_ECAM_QUIRK(1, 0),
++      ALTRA_ECAM_QUIRK(1, 1),
++      ALTRA_ECAM_QUIRK(1, 2),
++      ALTRA_ECAM_QUIRK(1, 3),
++      ALTRA_ECAM_QUIRK(1, 4),
++      ALTRA_ECAM_QUIRK(1, 5),
++      ALTRA_ECAM_QUIRK(1, 6),
++      ALTRA_ECAM_QUIRK(1, 7),
++      ALTRA_ECAM_QUIRK(1, 8),
++      ALTRA_ECAM_QUIRK(1, 9),
++      ALTRA_ECAM_QUIRK(1, 10),
++      ALTRA_ECAM_QUIRK(1, 11),
++      ALTRA_ECAM_QUIRK(1, 12),
++      ALTRA_ECAM_QUIRK(1, 13),
++      ALTRA_ECAM_QUIRK(1, 14),
++      ALTRA_ECAM_QUIRK(1, 15),
+ };
+ 
+ static char mcfg_oem_id[ACPI_OEM_ID_SIZE];
+--- a/drivers/pci/ecam.c
++++ b/drivers/pci/ecam.c
+@@ -164,4 +164,14 @@ struct pci_ecam_ops pci_32b_ops = {
+               .write          = pci_generic_config_write32,
+       }
+ };
++
++/* ECAM ops for 32-bit read only (non-compliant) */
++struct pci_ecam_ops pci_32b_read_ops = {
++      .bus_shift      = 20,
++      .pci_ops        = {
++              .map_bus        = pci_ecam_map_bus,
++              .read           = pci_generic_config_read32,
++              .write          = pci_generic_config_write,
++      }
++};
+ #endif
+--- a/include/linux/pci-ecam.h
++++ b/include/linux/pci-ecam.h
+@@ -51,6 +51,7 @@ extern struct pci_ecam_ops pci_generic_e
+ 
+ #if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
+ extern struct pci_ecam_ops pci_32b_ops;               /* 32-bit accesses only */
++extern struct pci_ecam_ops pci_32b_read_ops; /* 32-bit read only */
+ extern struct pci_ecam_ops hisi_pcie_ops;     /* HiSilicon */
+ extern struct pci_ecam_ops thunder_pem_ecam_ops; /* Cavium ThunderX 1.x & 2.x */
+ extern struct pci_ecam_ops pci_thunder_ecam_ops; /* Cavium ThunderX 1.x */

diff --git a/queue-5.4/series b/queue-5.4/series
index eeea807c4986e7dc40581026e84212786d326c69..d9851c122f8820094a90d12e05a1f4e509bd25ba 100644 (file)
--- a/queue-5.4/series
+++ b/queue-5.4/series
@@ -2,3 +2,4 @@ pci-pci-bridge-emul-fix-big-endian-support.patch
 pci-aardvark-indicate-error-in-val-when-config-read-fails.patch
 pci-pci-bridge-emul-add-pcie-root-capabilities-register.patch
 pci-aardvark-fix-reporting-crs-value.patch
+pci-acpi-add-ampere-altra-soc-mcfg-quirk.patch