drm/xe/xe3p_xpc: Skip compression tuning on platforms without flatccs

The compression overfetch tuning settings only apply to platforms that
support FlatCCS.  In Xe3p_XPC (and any future IPs that also lack
compression) some of the registers being adjusted by this tuning will
not exist or may have been repurposed for something else, so we should
take care not to try to program them.

Note that our xe_rtp_match_has_flatccs() function will also return false
on platforms that do have FlatCCS in the hardware design, but have
compression manually disabled in the BIOS.  On such platforms the
registers still exist (and it would be fine to continue programming
them), but they would have no effect, so skipping that tuning is also
safe.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
Link: https://lore.kernel.org/r/20251016-xe3p-v3-22-3dd173a3097a@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

diff --git a/drivers/gpu/drm/xe/xe_rtp.c b/drivers/gpu/drm/xe/xe_rtp.c
index 66707cc89ec9764abdb7ad31d2198285d2019125..ed509b1c8cfcdd0482812ff9d1ce99649650f742 100644 (file)
--- a/drivers/gpu/drm/xe/xe_rtp.c
+++ b/drivers/gpu/drm/xe/xe_rtp.c
@@ -378,3 +378,10 @@ bool xe_rtp_match_gt_has_discontiguous_dss_groups(const struct xe_device *xe,
 {
        return xe_gt_has_discontiguous_dss_groups(gt);
 }
+
+bool xe_rtp_match_has_flat_ccs(const struct xe_device *xe,
+                              const struct xe_gt *gt,
+                              const struct xe_hw_engine *hwe)
+{
+       return xe->info.has_flat_ccs;
+}

diff --git a/drivers/gpu/drm/xe/xe_rtp.h b/drivers/gpu/drm/xe/xe_rtp.h
index e5b8a9452e29eabbf2a46c750f968c0eb27fd6a4..ba5f940c0a961e10effd457c6d631de2170aa39e 100644 (file)
--- a/drivers/gpu/drm/xe/xe_rtp.h
+++ b/drivers/gpu/drm/xe/xe_rtp.h
@@ -491,4 +491,16 @@ bool xe_rtp_match_gt_has_discontiguous_dss_groups(const struct xe_device *xe,
                                                  const struct xe_gt *gt,
                                                  const struct xe_hw_engine *hwe);
 
+/**
+ * xe_rtp_match_has_flat_ccs - Match when platform has FlatCCS compression
+ * @xe: Device structure
+ * @gt: GT structure
+ * @hwe: Engine instance
+ *
+ * Returns: true if platform has FlatCCS compression, false otherwise
+ */
+bool xe_rtp_match_has_flat_ccs(const struct xe_device *xe,
+                              const struct xe_gt *gt,
+                              const struct xe_hw_engine *hwe);
+
 #endif

diff --git a/drivers/gpu/drm/xe/xe_tuning.c b/drivers/gpu/drm/xe/xe_tuning.c
index fd58ea5e78bf62f911c835cd9cee871964d2adf6..7c140d8cb1e07b662e203ae9b295c8073362424e 100644 (file)
--- a/drivers/gpu/drm/xe/xe_tuning.c
+++ b/drivers/gpu/drm/xe/xe_tuning.c
@@ -40,7 +40,8 @@ static const struct xe_rtp_entry_sr gt_tunings[] = {
                                   REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)))
        },
        { XE_RTP_NAME("Tuning: Compression Overfetch"),
-         XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)),
+         XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED),
+                      FUNC(xe_rtp_match_has_flat_ccs)),
          XE_RTP_ACTIONS(CLR(CCCHKNREG1, ENCOMPPERFFIX),
                         SET(CCCHKNREG1, L3CMPCTRL))
        },
@@ -58,12 +59,14 @@ static const struct xe_rtp_entry_sr gt_tunings[] = {
          XE_RTP_ACTIONS(SET(XE2LPM_L3SQCREG3, COMPPWOVERFETCHEN))
        },
        { XE_RTP_NAME("Tuning: L2 Overfetch Compressible Only"),
-         XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)),
+         XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED),
+                      FUNC(xe_rtp_match_has_flat_ccs)),
          XE_RTP_ACTIONS(SET(L3SQCREG2,
                             COMPMEMRD256BOVRFETCHEN))
        },
        { XE_RTP_NAME("Tuning: L2 Overfetch Compressible Only - media"),
-         XE_RTP_RULES(MEDIA_VERSION_RANGE(2000, XE_RTP_END_VERSION_UNDEFINED)),
+         XE_RTP_RULES(MEDIA_VERSION_RANGE(2000, XE_RTP_END_VERSION_UNDEFINED),
+                      FUNC(xe_rtp_match_has_flat_ccs)),
          XE_RTP_ACTIONS(SET(XE2LPM_L3SQCREG2,
                             COMPMEMRD256BOVRFETCHEN))
        },