--- /dev/null
+From 017d213f649c6775e4a4349e50a5631a4e4c7308 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 23 Mar 2012 14:44:47 -0400
+Subject: drm/radeon/kms/atom: force bpc to 8 for now
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit 017d213f649c6775e4a4349e50a5631a4e4c7308 upstream.
+
+Using the bpc (bits per color) specified by the monitor
+can cause problems in some cases. Until we get a better
+handle on how to deal with those cases, just use a bpc of 8.
+
+Reported-by: Lennert Buytenhek <buytenh@wantstofly.org>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Dave Airlie <airlied@redhat.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/atombios_crtc.c | 8 +++++---
+ drivers/gpu/drm/radeon/atombios_dp.c | 3 +++
+ drivers/gpu/drm/radeon/atombios_encoders.c | 4 ++--
+ 3 files changed, 10 insertions(+), 5 deletions(-)
+
+--- a/drivers/gpu/drm/radeon/atombios_crtc.c
++++ b/drivers/gpu/drm/radeon/atombios_crtc.c
+@@ -550,8 +550,8 @@ static u32 atombios_adjust_pll(struct dr
+ if (encoder->crtc == crtc) {
+ radeon_encoder = to_radeon_encoder(encoder);
+ connector = radeon_get_connector_for_encoder(encoder);
+- if (connector && connector->display_info.bpc)
+- bpc = connector->display_info.bpc;
++ /* if (connector && connector->display_info.bpc)
++ bpc = connector->display_info.bpc; */
+ encoder_mode = atombios_get_encoder_mode(encoder);
+ is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock);
+ if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
+@@ -922,7 +922,9 @@ static void atombios_crtc_set_pll(struct
+ struct radeon_connector_atom_dig *dig_connector =
+ radeon_connector->con_priv;
+ int dp_clock;
+- bpc = connector->display_info.bpc;
++
++ /* if (connector->display_info.bpc)
++ bpc = connector->display_info.bpc; */
+
+ switch (encoder_mode) {
+ case ATOM_ENCODER_MODE_DP_MST:
+--- a/drivers/gpu/drm/radeon/atombios_dp.c
++++ b/drivers/gpu/drm/radeon/atombios_dp.c
+@@ -405,10 +405,13 @@ static void dp_get_adjust_train(u8 link_
+ /* get bpc from the EDID */
+ static int convert_bpc_to_bpp(int bpc)
+ {
++#if 0
+ if (bpc == 0)
+ return 24;
+ else
+ return bpc * 3;
++#endif
++ return 24;
+ }
+
+ /* get the max pix clock supported by the link rate and lane num */
+--- a/drivers/gpu/drm/radeon/atombios_encoders.c
++++ b/drivers/gpu/drm/radeon/atombios_encoders.c
+@@ -537,7 +537,7 @@ atombios_dig_encoder_setup(struct drm_en
+ dp_clock = dig_connector->dp_clock;
+ dp_lane_count = dig_connector->dp_lane_count;
+ hpd_id = radeon_connector->hpd.hpd;
+- bpc = connector->display_info.bpc;
++ /* bpc = connector->display_info.bpc; */
+ }
+
+ /* no dig encoder assigned */
+@@ -1098,7 +1098,7 @@ atombios_external_encoder_setup(struct d
+ dp_lane_count = dig_connector->dp_lane_count;
+ connector_object_id =
+ (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
+- bpc = connector->display_info.bpc;
++ /* bpc = connector->display_info.bpc; */
+ }
+
+ memset(&args, 0, sizeof(args));
--- /dev/null
+From 81b279d80a63628e580c71a31d30a8c3b3047ad4 Mon Sep 17 00:00:00 2001
+From: Sekhar Nori <nsekhar@ti.com>
+Date: Sun, 11 Mar 2012 18:16:12 +0530
+Subject: gpio/davinci: fix enabling unbanked GPIO IRQs
+
+From: Sekhar Nori <nsekhar@ti.com>
+
+commit 81b279d80a63628e580c71a31d30a8c3b3047ad4 upstream.
+
+Unbanked GPIO IRQ handling code made a copy of just
+the irq_chip structure for GPIO IRQ lines which caused
+problems after the generic IRQ chip conversion because
+there was no valid irq_chip_type structure with the
+right "regs" populated. irq_gc_mask_set_bit() was
+therefore accessing random addresses.
+
+Fix it by making a copy of irq_chip_type structure
+instead. This will ensure sane register offsets.
+
+Reported-by: Jon Povey <Jon.Povey@racelogic.co.uk>
+Tested-by: Jon Povey <Jon.Povey@racelogic.co.uk>
+Signed-off-by: Sekhar Nori <nsekhar@ti.com>
+Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpio/gpio-davinci.c | 11 ++++++-----
+ 1 file changed, 6 insertions(+), 5 deletions(-)
+
+--- a/drivers/gpio/gpio-davinci.c
++++ b/drivers/gpio/gpio-davinci.c
+@@ -386,7 +386,7 @@ static int __init davinci_gpio_irq_setup
+ * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs.
+ */
+ if (soc_info->gpio_unbanked) {
+- static struct irq_chip gpio_irqchip_unbanked;
++ static struct irq_chip_type gpio_unbanked;
+
+ /* pass "bank 0" GPIO IRQs to AINTC */
+ chips[0].chip.to_irq = gpio_to_irq_unbanked;
+@@ -394,9 +394,10 @@ static int __init davinci_gpio_irq_setup
+
+ /* AINTC handles mask/unmask; GPIO handles triggering */
+ irq = bank_irq;
+- gpio_irqchip_unbanked = *irq_get_chip(irq);
+- gpio_irqchip_unbanked.name = "GPIO-AINTC";
+- gpio_irqchip_unbanked.irq_set_type = gpio_irq_type_unbanked;
++ gpio_unbanked = *container_of(irq_get_chip(irq),
++ struct irq_chip_type, chip);
++ gpio_unbanked.chip.name = "GPIO-AINTC";
++ gpio_unbanked.chip.irq_set_type = gpio_irq_type_unbanked;
+
+ /* default trigger: both edges */
+ g = gpio2regs(0);
+@@ -405,7 +406,7 @@ static int __init davinci_gpio_irq_setup
+
+ /* set the direct IRQs up to use that irqchip */
+ for (gpio = 0; gpio < soc_info->gpio_unbanked; gpio++, irq++) {
+- irq_set_chip(irq, &gpio_irqchip_unbanked);
++ irq_set_chip(irq, &gpio_unbanked.chip);
+ irq_set_handler_data(irq, &chips[gpio / 32]);
+ irq_set_status_flags(irq, IRQ_TYPE_EDGE_BOTH);
+ }
--- /dev/null
+From ab2dde9924dd1ddb791fa8b14aa52e1df681e20c Mon Sep 17 00:00:00 2001
+From: Sekhar Nori <nsekhar@ti.com>
+Date: Sun, 11 Mar 2012 18:16:11 +0530
+Subject: gpio/davinci: fix oops on unbanked gpio irq request
+
+From: Sekhar Nori <nsekhar@ti.com>
+
+commit ab2dde9924dd1ddb791fa8b14aa52e1df681e20c upstream.
+
+Unbanked GPIO irq setup code was overwriting chip_data leading
+to the following oops on request_irq()
+
+Unable to handle kernel paging request at virtual address febfffff
+pgd = c22dc000
+[febfffff] *pgd=00000000
+Internal error: Oops: 801 [#1] PREEMPT
+Modules linked in: mcu(+) edmak irqk cmemk
+CPU: 0 Not tainted (3.0.0-rc7+ #93)
+PC is at irq_gc_mask_set_bit+0x68/0x7c
+LR is at vprintk+0x22c/0x484
+pc : [<c0080c0c>] lr : [<c00457e0>] psr: 60000093
+sp : c33e3ba0 ip : c33e3af0 fp : c33e3bc4
+r10: c04555bc r9 : c33d4340 r8 : 60000013
+r7 : 0000002d r6 : c04555bc r5 : fec67010 r4 : 00000000
+r3 : c04734c8 r2 : fec00000 r1 : ffffffff r0 : 00000026
+Flags: nZCv IRQs off FIQs on Mode SVC_32 ISA ARM Segment user
+Control: 0005317f Table: 822dc000 DAC: 00000015
+Process modprobe (pid: 526, stack limit = 0xc33e2270)
+Stack: (0xc33e3ba0 to 0xc33e4000)
+3ba0: 00000000 c007d3d4 c33e3bcc c04555bc c04555bc c33d4340 c33e3bdc c33e3bc8
+3bc0: c007f5f8 c0080bb4 00000000 c04555bc c33e3bf4 c33e3be0 c007f654 c007f5c0
+3be0: 00000000 c04555bc c33e3c24 c33e3bf8 c007e6e8 c007f618 c01f2284 c0350af8
+3c00: c0405214 bf016c98 00000001 00000000 c33dc008 0000002d c33e3c54 c33e3c28
+3c20: c007e888 c007e408 00000001 c23ef880 c33dc000 00000000 c33dc080 c25caa00
+3c40: c0487498 bf017078 c33e3c94 c33e3c58 bf016b44 c007e7d4 bf017078 c33dc008
+3c60: c25caa08 c33dc008 c33e3c84 bf017484 c25caa00 c25caa00 c01f5f48 c25caa08
+3c80: c0496d60 bf017484 c33e3ca4 c33e3c98 c022a698 bf01692c c33e3cd4 c33e3ca8
+3ca0: c01f5d88 c022a688 00000000 bf017484 c25caa00 c25caa00 c01f5f48 c25caa08
+3cc0: c0496d60 00000000 c33e3cec c33e3cd8 c01f5f8c c01f5d10 00000000 c33e3cf0
+3ce0: c33e3d14 c33e3cf0 c01f5210 c01f5f58 c303cb48 c25ecf94 c25caa00 c25caa00
+3d00: c25caa34 c33e3dd8 c33e3d34 c33e3d18 c01f6044 c01f51b8 c0496d3c c25caa00
+3d20: c044e918 c33e3dd8 c33e3d44 c33e3d38 c01f4ff4 c01f5fcc c33e3d94 c33e3d48
+3d40: c01f3d10 c01f4fd8 00000000 c044e918 00000000 00000000 c01f52c0 c034d570
+3d60: c33e3d84 c33e3d70 c022bf84 c25caa00 00000000 c044e918 c33e3dd8 c25c2e00
+3d80: c0496d60 bf01763c c33e3db4 c33e3d98 c022b1a0 c01f384c c25caa00 c33e3dd8
+3da0: 00000000 c33e3dd8 c33e3dd4 c33e3db8 c022b27c c022b0e8 00000000 bf01763c
+3dc0: c0451c80 c33e3dd8 c33e3e34 c33e3dd8 bf016f60 c022b210 5f75636d 746e6f63
+3de0: 006c6f72 00000000 00000000 00000000 00000000 00000000 00000000 bf0174bc
+3e00: 00000000 00989680 00000000 00000020 c0451c80 c0451c80 bf0174dc c01f5eb0
+3e20: c33f0f00 bf0174dc c33e3e44 c33e3e38 c01f72f4 bf016e2c c33e3e74 c33e3e48
+3e40: c01f5d88 c01f72e4 00000000 c0451c80 c0451cb4 bf0174dc c01f5eb0 c33f0f00
+3e60: c0473100 00000000 c33e3e94 c33e3e78 c01f5f44 c01f5d10 00000000 c33e3e98
+3e80: bf0174dc c01f5eb0 c33e3ebc c33e3e98 c01f5534 c01f5ec0 c303c038 c3061c30
+3ea0: 00003cd8 00098258 bf0174dc c0462ac8 c33e3ecc c33e3ec0 c01f5bec c01f54dc
+3ec0: c33e3efc c33e3ed0 c01f4d30 c01f5bdc bf0173a0 c33e2000 00003cd8 00098258
+3ee0: bf0174dc c33e2000 c00301a4 bf019000 c33e3f1c c33e3f00 c01f6588 c01f4c8c
+3f00: 00003cd8 00098258 00000000 c33e2000 c33e3f2c c33e3f20 c01f777c c01f6524
+3f20: c33e3f3c c33e3f30 bf019014 c01f7740 c33e3f7c c33e3f40 c002f3ec bf019010
+3f40: 00000000 00003cd8 00098258 bf017518 00000000 00003cd8 00098258 bf017518
+3f60: 00000000 c00301a4 c33e2000 00000000 c33e3fa4 c33e3f80 c007b934 c002f3c4
+3f80: c00b307c c00b2f48 00003cd8 00000000 00000003 00000080 00000000 c33e3fa8
+3fa0: c0030020 c007b8b8 00003cd8 00000000 00098288 00003cd8 00098258 00098240
+3fc0: 00003cd8 00000000 00000003 00000080 00098008 00098028 00098288 00000001
+3fe0: be892998 be892988 00013d7c 40178740 60000010 00098288 09089041 00200845
+Backtrace:
+[<c0080ba4>] (irq_gc_mask_set_bit+0x0/0x7c) from [<c007f5f8>] (irq_enable+0x48/0x58)
+ r6:c33d4340 r5:c04555bc r4:c04555bc
+[<c007f5b0>] (irq_enable+0x0/0x58) from [<c007f654>] (irq_startup+0x4c/0x54)
+ r5:c04555bc r4:00000000
+[<c007f608>] (irq_startup+0x0/0x54) from [<c007e6e8>] (__setup_irq+0x2f0/0x3cc)
+ r5:c04555bc r4:00000000
+[<c007e3f8>] (__setup_irq+0x0/0x3cc) from [<c007e888>] (request_threaded_irq+0xc4/0x110)
+ r8:0000002d r7:c33dc008 r6:00000000 r5:00000001 r4:bf016c98
+[<c007e7c4>] (request_threaded_irq+0x0/0x110) from [<bf016b44>] (mcu_spi_probe+0x228/0x37c [mcu])
+[<bf01691c>] (mcu_spi_probe+0x0/0x37c [mcu]) from [<c022a698>] (spi_drv_probe+0x20/0x24)
+[<c022a678>] (spi_drv_probe+0x0/0x24) from [<c01f5d88>] (driver_probe_device+0x88/0x1b0)
+[<c01f5d00>] (driver_probe_device+0x0/0x1b0) from [<c01f5f8c>] (__device_attach+0x44/0x48)
+[<c01f5f48>] (__device_attach+0x0/0x48) from [<c01f5210>] (bus_for_each_drv+0x68/0x94)
+ r5:c33e3cf0 r4:00000000
+[<c01f51a8>] (bus_for_each_drv+0x0/0x94) from [<c01f6044>] (device_attach+0x88/0xa0)
+ r7:c33e3dd8 r6:c25caa34 r5:c25caa00 r4:c25caa00
+[<c01f5fbc>] (device_attach+0x0/0xa0) from [<c01f4ff4>] (bus_probe_device+0x2c/0x4c)
+ r7:c33e3dd8 r6:c044e918 r5:c25caa00 r4:c0496d3c
+[<c01f4fc8>] (bus_probe_device+0x0/0x4c) from [<c01f3d10>] (device_add+0x4d4/0x648)
+[<c01f383c>] (device_add+0x0/0x648) from [<c022b1a0>] (spi_add_device+0xc8/0x128)
+[<c022b0d8>] (spi_add_device+0x0/0x128) from [<c022b27c>] (spi_new_device+0x7c/0xb4)
+ r7:c33e3dd8 r6:00000000 r5:c33e3dd8 r4:c25caa00
+[<c022b200>] (spi_new_device+0x0/0xb4) from [<bf016f60>] (mcu_probe+0x144/0x224 [mcu])
+ r7:c33e3dd8 r6:c0451c80 r5:bf01763c r4:00000000
+[<bf016e1c>] (mcu_probe+0x0/0x224 [mcu]) from [<c01f72f4>] (platform_drv_probe+0x20/0x24)
+[<c01f72d4>] (platform_drv_probe+0x0/0x24) from [<c01f5d88>] (driver_probe_device+0x88/0x1b0)
+[<c01f5d00>] (driver_probe_device+0x0/0x1b0) from [<c01f5f44>] (__driver_attach+0x94/0x98)
+[<c01f5eb0>] (__driver_attach+0x0/0x98) from [<c01f5534>] (bus_for_each_dev+0x68/0x94)
+ r7:c01f5eb0 r6:bf0174dc r5:c33e3e98 r4:00000000
+[<c01f54cc>] (bus_for_each_dev+0x0/0x94) from [<c01f5bec>] (driver_attach+0x20/0x28)
+ r7:c0462ac8 r6:bf0174dc r5:00098258 r4:00003cd8
+[<c01f5bcc>] (driver_attach+0x0/0x28) from [<c01f4d30>] (bus_add_driver+0xb4/0x258)
+[<c01f4c7c>] (bus_add_driver+0x0/0x258) from [<c01f6588>] (driver_register+0x74/0x158)
+[<c01f6514>] (driver_register+0x0/0x158) from [<c01f777c>] (platform_driver_register+0x4c/0x60)
+ r7:c33e2000 r6:00000000 r5:00098258 r4:00003cd8
+[<c01f7730>] (platform_driver_register+0x0/0x60) from [<bf019014>] (mcu_init+0x14/0x20 [mcu])
+[<bf019000>] (mcu_init+0x0/0x20 [mcu]) from [<c002f3ec>] (do_one_initcall+0x38/0x170)
+[<c002f3b4>] (do_one_initcall+0x0/0x170) from [<c007b934>] (sys_init_module+0x8c/0x1a4)
+[<c007b8a8>] (sys_init_module+0x0/0x1a4) from [<c0030020>] (ret_fast_syscall+0x0/0x2c)
+ r7:00000080 r6:00000003 r5:00000000 r4:00003cd8
+Code: e1844003 e585400c e596300c e5932064 (e7814002)
+
+Fix the issue.
+
+Reported-by: Jon Povey <Jon.Povey@racelogic.co.uk>
+Signed-off-by: Sekhar Nori <nsekhar@ti.com>
+Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpio/gpio-davinci.c | 15 ++++++++++-----
+ 1 file changed, 10 insertions(+), 5 deletions(-)
+
+--- a/drivers/gpio/gpio-davinci.c
++++ b/drivers/gpio/gpio-davinci.c
+@@ -313,10 +313,16 @@ static int gpio_to_irq_unbanked(struct g
+ return -ENODEV;
+ }
+
+-static int gpio_irq_type_unbanked(struct irq_data *d, unsigned trigger)
++static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger)
+ {
+- struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
+- u32 mask = (u32) irq_data_get_irq_handler_data(d);
++ struct davinci_gpio_controller *d;
++ struct davinci_gpio_regs __iomem *g;
++ struct davinci_soc_info *soc_info = &davinci_soc_info;
++ u32 mask;
++
++ d = (struct davinci_gpio_controller *)data->handler_data;
++ g = (struct davinci_gpio_regs __iomem *)d->regs;
++ mask = __gpio_mask(data->irq - soc_info->gpio_irq);
+
+ if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
+ return -EINVAL;
+@@ -400,8 +406,7 @@ static int __init davinci_gpio_irq_setup
+ /* set the direct IRQs up to use that irqchip */
+ for (gpio = 0; gpio < soc_info->gpio_unbanked; gpio++, irq++) {
+ irq_set_chip(irq, &gpio_irqchip_unbanked);
+- irq_set_handler_data(irq, (void *)__gpio_mask(gpio));
+- irq_set_chip_data(irq, (__force void *)g);
++ irq_set_handler_data(irq, &chips[gpio / 32]);
+ irq_set_status_flags(irq, IRQ_TYPE_EDGE_BOTH);
+ }
+
--- /dev/null
+From 8276536cec38bc6bde30d0aa67716f22b9b9705a Mon Sep 17 00:00:00 2001
+From: Tarun Kanti DebBarma <tarun.kanti@ti.com>
+Date: Fri, 25 Nov 2011 15:27:37 +0530
+Subject: gpio/omap: fix _set_gpio_irqenable implementation
+
+From: Tarun Kanti DebBarma <tarun.kanti@ti.com>
+
+commit 8276536cec38bc6bde30d0aa67716f22b9b9705a upstream.
+
+This function should be capable of both enabling and disabling interrupts
+based upon the *enable* parameter. Right now the function only enables
+the interrupt and *enable* is not used at all. So add the interrupt
+disable capability also using the parameter.
+
+Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
+Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
+Acked-by: Felipe Balbi <balbi@ti.com>
+Reviewed-by: Kevin Hilman <khilman@ti.com>
+Signed-off-by: Kevin Hilman <khilman@ti.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpio/gpio-omap.c | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+--- a/drivers/gpio/gpio-omap.c
++++ b/drivers/gpio/gpio-omap.c
+@@ -508,7 +508,10 @@ static void _disable_gpio_irqbank(struct
+
+ static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
+ {
+- _enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
++ if (enable)
++ _enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
++ else
++ _disable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
+ }
+
+ /*
--- /dev/null
+From d2cb87c23e8514ca49c85adc5924999927bb9494 Mon Sep 17 00:00:00 2001
+From: Mark Brown <broonie@opensource.wolfsonmicro.com>
+Date: Mon, 20 Feb 2012 21:32:32 +0000
+Subject: mfd: Test for jack detection when deciding if wm8994 should suspend
+
+From: Mark Brown <broonie@opensource.wolfsonmicro.com>
+
+commit d2cb87c23e8514ca49c85adc5924999927bb9494 upstream.
+
+The jack detection on WM1811 is often required during system suspend, add
+it as another check when deciding if we should suspend.
+
+Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
+Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/mfd/wm8994-core.c | 14 ++++++++++++++
+ 1 file changed, 14 insertions(+)
+
+--- a/drivers/mfd/wm8994-core.c
++++ b/drivers/mfd/wm8994-core.c
+@@ -270,6 +270,20 @@ static int wm8994_suspend(struct device
+ break;
+ }
+
++ switch (wm8994->type) {
++ case WM1811:
++ ret = wm8994_reg_read(wm8994, WM8994_ANTIPOP_2);
++ if (ret < 0) {
++ dev_err(dev, "Failed to read jackdet: %d\n", ret);
++ } else if (ret & WM1811_JACKDET_MODE_MASK) {
++ dev_dbg(dev, "CODEC still active, ignoring suspend\n");
++ return 0;
++ }
++ break;
++ default:
++ break;
++ }
++
+ /* Disable LDO pulldowns while the device is suspended if we
+ * don't know that something will be driving them. */
+ if (!wm8994->ldo_ena_always_driven)
ext4-check-for-zero-length-extent.patch
vfs-fix-d_ancestor-case-in-d_materialize_unique.patch
arm-tegra-select-required-cpu-and-l2-errata-options.patch
+gpio-omap-fix-_set_gpio_irqenable-implementation.patch
+gpio-davinci-fix-oops-on-unbanked-gpio-irq-request.patch
+gpio-davinci-fix-enabling-unbanked-gpio-irqs.patch
+mfd-test-for-jack-detection-when-deciding-if-wm8994-should-suspend.patch
+drm-radeon-kms-atom-force-bpc-to-8-for-now.patch
projects / thirdparty / kernel / stable-queue.git / commitdiff
