s390x: Update instruction list with arch15 insns

Recent commits in Binutils added arch15 instructions to s390-opc.txt.
Since then, the script s390-check-opcodes.pl complains about many insns
that are not known to Valgrind.

Update Valgrind's instruction list to be in synch with Binutils again.
Add the new instructions to s390-opcodes.csv and declare them as "not
implemented".

diff --git a/VEX/priv/guest_s390_toIR.c b/VEX/priv/guest_s390_toIR.c
index b6e8e5997e12e0fc03cf735f9f2ca669a5034858..6da5996452d2de7f4710f4e34ac139c6492532cf 100644 (file)
--- a/VEX/priv/guest_s390_toIR.c
+++ b/VEX/priv/guest_s390_toIR.c
@@ -20675,6 +20675,10 @@ s390_decode_4byte_and_irgen(const UChar *bytes)
                                       RRF4_r1(ovl), RRF4_r2(ovl)); goto ok;
    case 0xb967: s390_format_RRF_R0RR2(s390_irgen_NXGRK, RRF4_r3(ovl),
                                       RRF4_r1(ovl), RRF4_r2(ovl)); goto ok;
+   case 0xb968: /* CLZG */ goto unimplemented;
+   case 0xb969: /* CTZG */ goto unimplemented;
+   case 0xb96c: /* BEXTG */ goto unimplemented;
+   case 0xb96d: /* BDEPG */ goto unimplemented;
    case 0xb972: s390_format_RRF_U0RR(s390_irgen_CRT, RRF2_m3(ovl),
                                      RRF2_r1(ovl), RRF2_r2(ovl),
                                      S390_XMNM_CAB); goto ok;
@@ -21279,6 +21283,16 @@ s390_decode_6byte_and_irgen(const UChar *bytes)
                                                 RXY_x2(ovl), RXY_b2(ovl),
                                                 RXY_dl2(ovl),
                                                 RXY_dh2(ovl));  goto ok;
+   case 0xe30000000060ULL: /* LXAB */ goto unimplemented;
+   case 0xe30000000061ULL: /* LLXAB */ goto unimplemented;
+   case 0xe30000000062ULL: /* LXAH */ goto unimplemented;
+   case 0xe30000000063ULL: /* LLXAH */ goto unimplemented;
+   case 0xe30000000064ULL: /* LXAF */ goto unimplemented;
+   case 0xe30000000065ULL: /* LLXAF */ goto unimplemented;
+   case 0xe30000000066ULL: /* LXAG */ goto unimplemented;
+   case 0xe30000000067ULL: /* LLXAG */ goto unimplemented;
+   case 0xe30000000068ULL: /* LXAQ */ goto unimplemented;
+   case 0xe30000000069ULL: /* LLXAQ */ goto unimplemented;
    case 0xe30000000070ULL: s390_format_RXY_RRRD(s390_irgen_STHY, RXY_r1(ovl),
                                                 RXY_x2(ovl), RXY_b2(ovl),
                                                 RXY_dl2(ovl),
@@ -21536,6 +21550,8 @@ s390_decode_6byte_and_irgen(const UChar *bytes)
                                                 VRS_d2(ovl),
                                                 VRS_rxb(ovl));  goto ok;
    case 0xe60000000049ULL: /* VLIP */ goto unimplemented;
+   case 0xe6000000004aULL: /* VCVDQ */ goto unimplemented;
+   case 0xe6000000004eULL: /* VCVBQ */ goto unimplemented;
    case 0xe60000000050ULL: /* VCVB */ goto unimplemented;
    case 0xe60000000051ULL: /* VCLZDP */ goto unimplemented;
    case 0xe60000000052ULL: /* VCVBG */ goto unimplemented;
@@ -21580,6 +21596,7 @@ s390_decode_6byte_and_irgen(const UChar *bytes)
    case 0xe6000000007cULL: /* VSCSHP */ goto unimplemented;
    case 0xe6000000007dULL: /* VCSPH */ goto unimplemented;
    case 0xe6000000007eULL: /* VSDP */ goto unimplemented;
+   case 0xe6000000007fULL: /* VTZ */ goto unimplemented;
    case 0xe70000000000ULL: s390_format_VRX_VRRDM(s390_irgen_VLEB, VRX_v1(ovl),
                                                  VRX_x2(ovl), VRX_b2(ovl),
                                                  VRX_d2(ovl), VRX_m3(ovl),
@@ -21720,6 +21737,7 @@ s390_decode_6byte_and_irgen(const UChar *bytes)
    case 0xe70000000053ULL: s390_format_VRR_VVM(s390_irgen_VCLZ, VRR_v1(ovl),
                                                VRR_v2(ovl), VRR_m4(ovl),
                                                VRR_rxb(ovl));  goto ok;
+   case 0xe70000000054ULL: /* VGEM */ goto unimplemented;
    case 0xe70000000056ULL: s390_format_VRR_VV(s390_irgen_VLR, VRR_v1(ovl),
                                               VRR_v2(ovl), VRR_rxb(ovl));  goto ok;
    case 0xe7000000005cULL: s390_format_VRR_VVMM(s390_irgen_VISTR, VRR_v1(ovl),
@@ -21836,6 +21854,8 @@ s390_decode_6byte_and_irgen(const UChar *bytes)
                                                  VRId_v2(ovl), VRId_v3(ovl),
                                                  VRId_i4(ovl),
                                                  VRId_rxb(ovl));  goto ok;
+   case 0xe70000000088ULL: /* VEVAL */ goto unimplemented;
+   case 0xe70000000089ULL: /* VBLEND */ goto unimplemented;
    case 0xe7000000008aULL: s390_format_VRR_VVVVMM(s390_irgen_VSTRC, VRRd_v1(ovl),
                                                   VRRd_v2(ovl), VRRd_v3(ovl),
                                                   VRRd_v4(ovl), VRRd_m5(ovl),
@@ -21930,6 +21950,10 @@ s390_decode_6byte_and_irgen(const UChar *bytes)
                                                   VRRd_v2(ovl), VRRd_v3(ovl),
                                                   VRRd_v4(ovl), VRRd_m5(ovl),
                                                   VRRd_rxb(ovl));  goto ok;
+   case 0xe700000000b0ULL: /* VDL */ goto unimplemented;
+   case 0xe700000000b1ULL: /* VRL */ goto unimplemented;
+   case 0xe700000000b2ULL: /* VD */ goto unimplemented;
+   case 0xe700000000b3ULL: /* VR */ goto unimplemented;
    case 0xe700000000b4ULL: s390_format_VRR_VVVM(s390_irgen_VGFM, VRR_v1(ovl),
                                                 VRR_v2(ovl), VRR_r3(ovl),
                                                 VRR_m4(ovl), VRR_rxb(ovl));  goto ok;
@@ -22136,6 +22160,7 @@ s390_decode_6byte_and_irgen(const UChar *bytes)
                                                 RSY_r3(ovl), RSY_b2(ovl),
                                                 RSY_dl2(ovl),
                                                 RSY_dh2(ovl));  goto ok;
+   case 0xeb0000000016ULL: /* PFCR */ goto unimplemented;
    case 0xeb000000001cULL: s390_format_RSY_RRRD(s390_irgen_RLLG, RSY_r1(ovl),
                                                 RSY_r3(ovl), RSY_b2(ovl),
                                                 RSY_dl2(ovl),
@@ -22772,6 +22797,9 @@ s390_decode_6byte_and_irgen(const UChar *bytes)
    case 0xc802ULL: /* CSST */ goto unimplemented;
    case 0xc804ULL: /* LPD */ goto unimplemented;
    case 0xc805ULL: /* LPDG */ goto unimplemented;
+   case 0xc806ULL: /* CAL */ goto unimplemented;
+   case 0xc807ULL: /* CALG */ goto unimplemented;
+   case 0xc80fULL: /* CALGF */ goto unimplemented;
    case 0xcc06ULL:  s390_format_RIL_RP(s390_irgen_BRCTH, RIL_r1(ovl),
                                        RIL_i2(ovl));  goto ok;
    case 0xcc08ULL: s390_format_RIL_RI(s390_irgen_AIH, RIL_r1(ovl),

diff --git a/auxprogs/s390-check-opcodes.pl b/auxprogs/s390-check-opcodes.pl
index 52325beaa143bccacc7d40a7c46f9232a273acc5..474bb3a7e8a36a1e4938af8c3d3471ae7447663c 100755 (executable)
--- a/auxprogs/s390-check-opcodes.pl
+++ b/auxprogs/s390-check-opcodes.pl
@@ -46,24 +46,24 @@ my %toir_implemented = ();
 my %toir_decoded = ();
 my %toir_format = ();
 my %known_arch = map {($_ => 1)}
-    qw(g5 z900 z990 z9-109 z9-ec z10 z196 zEC12 z13 arch12 arch13 arch14);
+    qw(g5 z900 z990 z9-109 z9-ec z10 z196 zEC12 z13 arch12 arch13 arch14 arch15);
 
 # Patterns for identifying certain extended mnemonics that shall be
 # skipped in "s390-opc.txt" and "s390-opcodes.csv".
 
-my @extended_mnemonics = (
-    "bi",                      # extended mnemonic for bic
+my @extended_mnemonics = (      # Base mnemonic(s)
+    "bi",                       # bic
     'brul?',
-    'jc',                      # brc
+    'jc',                       # brc
     'jasl?',
     'jct[gh]?',
     'jg?nop',
     'jxleg?',
     'jxhg?',
     'l[de]rv',
-    'lfi',                     # iilf
-    'llg[fh]i',                        # llilf, llill
-    'notg?r',                  # nork, nogrk
+    'lfi',                      # iilf
+    'llg[fh]i',                 # llilf, llill
+    'notg?r',                   # nork, nogrk
     'risbgn?z',
     'risb[hl]gz',
     'r[onx]sbgt',
@@ -72,17 +72,19 @@ my @extended_mnemonics = (
     "vacc[bhfgq]",
     "vacccq",
     "vacq",
-    "vavgl*[bhfg]",
+    "vavgl?[bhfgq]",            # vavg, vavgl
+    "vblend[bhfgq]",            # vblend
     "vcdl*gb",
     'vcfp[sl]',
     '[vw]cel?fb',
     'vc[sl]fp',
     '[vw]cl?feb',
-    "vceq[bhfg]s*",
-    "vchl*[bhfg]s*",
+    "vceq[bhfgq]s?",            # vceq
+    "vchl?[bhfgq]s?",           # vch, vchl
     "vcl*gdb",
-    "vc[lt]z[bhfg]",
-    "vecl*[bhfg]",
+    "vc[lt]z[bhfgq]",           # vclz, vctz
+    "vdl?[fgq]",                # vd, vdl
+    "vecl?[bhfgq]",             # vec, vecl
     "verim[bhfg]",
     "verllv*[bhfg]",
     "veslv*[bhfg]",
@@ -111,12 +113,13 @@ my @extended_mnemonics = (
     "vfpso[sd]b",
     "vfsq*[sd]b",
     "vftci[sd]b",
+    "vgem[bfghq]",              # vgem
     "vgfma*[bhfg]",
     "vgm[bhfg]",
     "vistr[bhfg]s*",
     'vlbr[hfgq]',
     'vlbrrep[hfg]',
-    "vlc[bhfg]",
+    "vlc[bhfgq]",               # vlc
     "[vw]ldeb",
     "[vw]ledb",
     'vler[hfg]',
@@ -124,15 +127,15 @@ my @extended_mnemonics = (
     'vllebrz[hfge]',
     "vllez[bhfg]",
     "vllezlf",
-    "vlp[bhfg]",
+    "vlp[bhfgq]",               # vlp
     "vlrep[bhfg]",
     "vlvg[bhfg]",
-    "vmal?[eoh][bhfg]",
-    "vmal(b|hw|f)",
-    "vml(b|hw|f)",
-    "vml?(o|e)[bhf]",
-    "vml?h[bhf]",
-    "vm[nx]l*[bhfg]",
+    "vmal?[eoh][bhfgq]",        # vmae, vmale, vmao, vmalo, vmah, vmalh
+    "vmal(b|hw|f|g|q)",         # vmal
+    "vml(b|hw|f|g|q)",          # vml
+    "vml?(o|e)[bhfg]",          # vmo, vme
+    "vml?h[bhfgq]",             # vmh, vmlh
+    "vm[nx]l*[bhfgq]",          # vmn, vmnl, vmx, vmxl
     "vmr[lh][bhfg]",
     "vmslg",
     "vnot",
@@ -140,22 +143,22 @@ my @extended_mnemonics = (
     "vpkl*[bhfg]",
     "vpkl*s*[bhfg]s*",
     "vpopct[bhfg]",
+    "vrl?[fgq]",                # vr, vrl
     "vrepi*[bhgf]",
     "vs[bhfgq]",
     "vsbcbiq",
     "vsbiq",
     "vscbi[bhfgq]",
-    "vsch[sdx]p",              # vschp (short/long/extended)
+    "vsch[sdx]p",               # vschp
     "vseg[bfh]",
     'vstbr[hfgq]',
     'vster[hfg]',
     "vstrcz*[bhf]s*",
     'vstrsz?[bhf]',
     "vsum(b|gh|gf|h|qf|qg)",
-    "vuplh[bhf]",
-    "vuph[bhf]",
-    "vupl(b|hw|f)",
-    "vupll[bhf]",
+    "vupl?h[bhfg]",             # vuph, vuplh
+    "vupl(b|hw|f|g)",           # vupl
+    "vupll[bhfg]",              # vupll
     "wcdl*gb",
     "wcl*gdb",
     "wfa[sdx]b",
@@ -172,7 +175,7 @@ my @extended_mnemonics = (
     "wftci[sdx]b",
     "wfsq*[sdx]b",
     "vl(ed|de)",
-    "prno"                     # alternate mnemonic for ppno
+    "prno"                      # ppno
     );
 
 # Compile excluded mnemonics into one regular expression to optimize

diff --git a/docs/internals/s390-opcodes.csv b/docs/internals/s390-opcodes.csv
index 2b6fae36dbc98ed01a7c64733e2f9b3a7b1446ff..75baaf15ad31f06cf748df2203428c6bbcf4c613 100644 (file)
--- a/docs/internals/s390-opcodes.csv
+++ b/docs/internals/s390-opcodes.csv
@@ -1765,3 +1765,73 @@ lpswey,"load PSW extended",N/A,"privileged instruction"
 lbear,"load bear",N/A,"privileged instruction"
 stbear,"store bear",N/A,"privileged instruction"
 qpaci,"query processor activity counter information",N/A,"privileged instruction"
+bdepg,"bit deposit","not implemented",arch15
+bextg,"bit extract","not implemented",arch15
+cal,"compare and load 32","not implemented",arch15
+calg,"compare and load 64","not implemented",arch15
+calgf,"compare and load 64<32","not implemented",arch15
+clzg,"count leading zeros","not implemented",arch15
+ctzg,"count trailing zeros","not implemented",arch15
+llxab,"load logical indexed address (shift left 0)","not implemented",arch15
+llxah,"load logical indexed address (shift left 1)","not implemented",arch15
+llxaf,"load logical indexed address (shift left 2)","not implemented",arch15
+llxag,"load logical indexed address (shift left 3)","not implemented",arch15
+llxaq,"load logical indexed address (shift left 4)","not implemented",arch15
+lxab,"load indexed address (shift left 0)","not implemented",arch15
+lxah,"load indexed address (shift left 1)","not implemented",arch15
+lxaf,"load indexed address (shift left 2)","not implemented",arch15
+lxag,"load indexed address (shift left 3)","not implemented",arch15
+lxaq,"load indexed address (shift left 4)","not implemented",arch15
+pfcr,"perform functions with concurrent results","not implemented",arch15
+vblend,"vector blend","not implemented",arch15
+vcvbq,"vector convert to binary 128 bit","not implemented",arch15
+vcvdq,"vector convert to decimal 128 bit","not implemented",arch15
+vd,"vector divide","not implemented",arch15
+vdl,"vector divide logical","not implemented",arch15
+veval,"vector evaluate","not implemented",arch15
+vgem,"vector generate element masks","not implemented",arch15
+vr,"vector remainder","not implemented",arch15
+vrl,"vector remainder logical","not implemented",arch15
+vtz,"vector test zoned","not implemented",arch15
+vavgq,"vector average quadword","not implemented",arch15
+vavglq,"vector average logical quadword","not implemented",arch15
+vecq,"vector element compare quadword","not implemented",arch15
+veclq,"vector element compare logical quadword","not implemented",arch15
+vceqq,"vector compare equal quadword","not implemented",arch15
+vceqqs,"vector compare equal quadword","not implemented",arch15
+vchq,"vector compare high quadword","not implemented",arch15
+vchqs,"vector compare high quadword","not implemented",arch15
+vchlq,"vector compare high logical quadword","not implemented",arch15
+vchlqs,"vector compare high logical quadword","not implemented",arch15
+vclzq,"vector count leading zeros quadword","not implemented",arch15
+vctzq,"vector count trailing zeros quadword","not implemented",arch15
+vlcq,"vector load complement quadword","not implemented",arch15
+vlpq,"vector load positive quadword","not implemented",arch15
+vmxq,"vector maximum quadword","not implemented",arch15
+vmxlq,"vector maximum logical quadword","not implemented",arch15
+vmnq,"vector minimum quadword","not implemented",arch15
+vmnlq,"vector minimum logical quadword","not implemented",arch15
+vmalg,"vector multiply and add low doubleword","not implemented",arch15
+vmalq,"vector multiply and add low quadword","not implemented",arch15
+vmahg,"vector multiply and add high doubleword","not implemented",arch15
+vmahq,"vector multiply and add high quadword","not implemented",arch15
+vmalhg,"vector multiply and add logical high doubleword","not implemented",arch15
+vmalhq,"vector multiply and add logical high quadword","not implemented",arch15
+vmaeg,"vector multiply and add even doubleword","not implemented",arch15
+vmaleg,"vector multiply and add logical even doubleword","not implemented",arch15
+vmaog,"vector multiply and add odd doubleword","not implemented",arch15
+vmalog,"vector multiply and add logical odd doubleword","not implemented",arch15
+vmhg,"vector multiply high doubleword","not implemented",arch15
+vmhq,"vector multiply high quadword","not implemented",arch15
+vmlhg,"vector multiply logical high doubleword","not implemented",arch15
+vmlhq,"vector multiply logical high quadword","not implemented",arch15
+vmlg,"vector multiply low doubleword","not implemented",arch15
+vmlq,"vector multiply low quadword","not implemented",arch15
+vmeg,"vector multiply even doubleword","not implemented",arch15
+vmleg,"vector multiply logical even doubleword","not implemented",arch15
+vmog,"vector multiply odd doubleword","not implemented",arch15
+vmlog,"vector multiply logical odd doubleword","not implemented",arch15
+vuphg,"vector unpack high doubleword","not implemented",arch15
+vuplhg,"vector unpack logical high doubleword","not implemented",arch15
+vuplg,"vector unpack low doubleword","not implemented",arch15
+vupllg,"vector unpack logical low doubleword","not implemented",arch15