RISC-V: Add implication from the XTheadZvamo extension

T-Head/XuanTie's vector extension documentation states that their vector
extensions are based on the standard vector extension draft,
version 0.7.1.

In that draft, it is rare to see dependencies between extensions as
in the ratified version ... except: "Zvamo" -> "Zaamo".

cf. <https://github.com/riscvarchive/riscv-v-spec/releases/tag/0.7.1>

> If vector AMO instructions are supported, then the scalar Zaamo
> instructions (atomic operations from the standard A extension)
> must be present.

Note that using the words like "imply" or "depend" for extensions
weren't a common practice to represent dependencies between extensions
at the time the documentation was created.

The "Zaamo" was not ratified as an extension at the time but this is a
subset of the "A" extension and defines scalar AMO operations (while
"Zvamo" -- NOT in the ratified specification -- defines vector AMO ops).

The important part is that the T-Head/XuanTie's documentation just
states that the "Zvamo" (draft) extension is renamed to "XTheadZvamo".
It means, this implication should have been preserved in some way.

> The extension Zvamo is renamed to XTheadZvamo.

cf. <https://github.com/XUANTIE-RV/thead-extension-spec/blob/2.3.0/xtheadvector.adoc>

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_implicit_subsets): Add implication
	"XTheadZvamo" -> "Zaamo".

gas/ChangeLog:

	* testsuite/gas/riscv/imply.s: Add "XTheadZvamo" implication.
	* testsuite/gas/riscv/imply.d: Ditto.

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 2487beeecc5659aa882e52c7f50f3704121bf5b2..007eedb3b239a7322271a28c7c0a09a18e6e9eef 100644 (file)
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1207,6 +1207,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"xsfvfnrclipxfqf", "+zve32f", check_implicit_always},
 
   {"xtheadvector", "+zicsr", check_implicit_always},
+  {"xtheadzvamo", "+zaamo", check_implicit_always},
 
   {"v", "+zve64d,+zvl128b", check_implicit_always},
   {"zvfh", "+zvfhmin,+zfhmin", check_implicit_always},

diff --git a/gas/testsuite/gas/riscv/imply.d b/gas/testsuite/gas/riscv/imply.d
index 58f13e488cfe5bb17fb810ac98bd3c8692cf310f..aa9c1c0458feff974b962119b2432fde29de35cd 100644 (file)
--- a/gas/testsuite/gas/riscv/imply.d
+++ b/gas/testsuite/gas/riscv/imply.d
@@ -23,6 +23,7 @@ SYMBOL TABLE:
 [0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zicsr2p0_zve32x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0
 [0-9a-f]+ l       .text        0+000 \$xrv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvl32b1p0_xsfvfnrclipxfqf1p0
 [0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zicsr2p0_xtheadvector1p0
+[0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zaamo1p0_xtheadzvamo1p0
 [0-9a-f]+ l       .text        0+000 \$xrv32i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0
 [0-9a-f]+ l       .text        0+000 \$xrv32i2p1_f2p2_zicsr2p0_zfhmin1p0_zve32f1p0_zve32x1p0_zvfh1p0_zvfhmin1p0_zvl32b1p0
 [0-9a-f]+ l       .text        0+000 \$xrv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfhmin1p0_zvl32b1p0

diff --git a/gas/testsuite/gas/riscv/imply.s b/gas/testsuite/gas/riscv/imply.s
index fc5cd5007754d4937c6ba88516e11ce28644fc67..be3c420a9da60fc3606007e01624475c897145b5 100644 (file)
--- a/gas/testsuite/gas/riscv/imply.s
+++ b/gas/testsuite/gas/riscv/imply.s
@@ -26,6 +26,7 @@ imply xsfvqmaccdod
 imply xsfvfnrclipxfqf
 
 imply xtheadvector
+imply xtheadzvamo
 
 imply v
 imply zvfh