net/mlx5: HWS, fix definer's HWS_SET32 macro for negative offset

When bit offset for HWS_SET32 macro is negative,
UBSAN complains about the shift-out-of-bounds:

  UBSAN: shift-out-of-bounds in
  drivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c:177:2
  shift exponent -8 is negative

Fixes: 74a778b4a63f ("net/mlx5: HWS, added definers handling")
Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
Reviewed-by: Erez Shitrit <erezsh@nvidia.com>
Reviewed-by: Mark Bloch <mbloch@nvidia.com>
Signed-off-by: Tariq Toukan <tariqt@nvidia.com>
Link: https://patch.msgid.link/20250102181415.1477316-12-tariqt@nvidia.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c
index 8fe96eb76baff7791cdba8eea1abeced7127be3d..10ece7df1cfaff904b9b9424ee1c32cecd12cfd8 100644 (file)
--- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c
@@ -70,7 +70,7 @@
                        u32 second_dw_mask = (mask) & ((1 << _bit_off) - 1); \
                        _HWS_SET32(p, (v) >> _bit_off, byte_off, 0, (mask) >> _bit_off); \
                        _HWS_SET32(p, (v) & second_dw_mask, (byte_off) + DW_SIZE, \
-                                   (bit_off) % BITS_IN_DW, second_dw_mask); \
+                                   (bit_off + BITS_IN_DW) % BITS_IN_DW, second_dw_mask); \
                } else { \
                        _HWS_SET32(p, v, byte_off, (bit_off), (mask)); \
                } \