3.0-stable patches

added patches:
	arm-orion-fix-orion5x-gpio-regression-from-mpp-cleanup.patch
	arm-orion-fix-usb-phy-for-orion5x.patch
	omap-4430sdp-panda-use-gpio_free_array-to-free-hdmi-gpios.patch

diff --git a/queue-3.0/arm-orion-fix-orion5x-gpio-regression-from-mpp-cleanup.patch b/queue-3.0/arm-orion-fix-orion5x-gpio-regression-from-mpp-cleanup.patch
new file mode 100644 (file)
index 0000000..7db4333
--- /dev/null
+++ b/queue-3.0/arm-orion-fix-orion5x-gpio-regression-from-mpp-cleanup.patch
@@ -0,0 +1,950 @@
+From b06540371063f0f07aafc1d1ac5e974da85c973c Mon Sep 17 00:00:00 2001
+From: Andrew Lunn <andrew@lunn.ch>
+Date: Wed, 8 Feb 2012 15:52:07 +0100
+Subject: ARM: orion: Fix Orion5x GPIO regression from MPP cleanup
+
+From: Andrew Lunn <andrew@lunn.ch>
+
+commit b06540371063f0f07aafc1d1ac5e974da85c973c upstream.
+
+Patchset "ARM: orion: Refactor the MPP code common in the orion
+platform" broke at least Orion5x based platforms. These platforms have
+pins configured as GPIO when the selector is not 0x0. However the
+common code assumes the selector is always 0x0 for a GPIO lines. It
+then ignores the GPIO bits in the MPP definitions, resulting in that
+Orion5x machines cannot correctly configure there GPIO lines.
+
+The Fix removes the assumption that the selector is always 0x0.
+In order that none GPIO configurations are correctly blocked,
+Kirkwood and mv78xx0 MPP definitions are corrected to only set the
+GPIO bits for GPIO configurations.
+
+This third version, which does not contain any whitespace changes,
+and is rebased on v3.3-rc2.
+
+Signed-off-by: Andrew Lunn <andrew@lunn.ch>
+Acked-by: Nicolas Pitre <nico@linaro.org>
+Signed-off-by: Olof Johansson <olof@lixom.net>
+
+
+---
+ arch/arm/mach-kirkwood/mpp.h |  320 +++++++++++++++++++++----------------------
+ arch/arm/mach-mv78xx0/mpp.h  |  226 +++++++++++++++---------------
+ arch/arm/plat-orion/mpp.c    |    3 
+ 3 files changed, 274 insertions(+), 275 deletions(-)
+
+--- a/arch/arm/mach-kirkwood/mpp.h
++++ b/arch/arm/mach-kirkwood/mpp.h
+@@ -31,313 +31,313 @@
+ #define MPP_F6282_MASK                MPP(  0, 0x0, 0, 0, 0,   0,   0,   0,   1 )
+ 
+ #define MPP0_GPIO             MPP(  0, 0x0, 1, 1, 1,   1,   1,   1,   1 )
+-#define MPP0_NF_IO2           MPP(  0, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+-#define MPP0_SPI_SCn          MPP(  0, 0x2, 0, 1, 1,   1,   1,   1,   1 )
++#define MPP0_NF_IO2           MPP(  0, 0x1, 0, 0, 1,   1,   1,   1,   1 )
++#define MPP0_SPI_SCn          MPP(  0, 0x2, 0, 0, 1,   1,   1,   1,   1 )
+ 
+ #define MPP1_GPO              MPP(  1, 0x0, 0, 1, 1,   1,   1,   1,   1 )
+-#define MPP1_NF_IO3           MPP(  1, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+-#define MPP1_SPI_MOSI         MPP(  1, 0x2, 0, 1, 1,   1,   1,   1,   1 )
++#define MPP1_NF_IO3           MPP(  1, 0x1, 0, 0, 1,   1,   1,   1,   1 )
++#define MPP1_SPI_MOSI         MPP(  1, 0x2, 0, 0, 1,   1,   1,   1,   1 )
+ 
+ #define MPP2_GPO              MPP(  2, 0x0, 0, 1, 1,   1,   1,   1,   1 )
+-#define MPP2_NF_IO4           MPP(  2, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+-#define MPP2_SPI_SCK          MPP(  2, 0x2, 0, 1, 1,   1,   1,   1,   1 )
++#define MPP2_NF_IO4           MPP(  2, 0x1, 0, 0, 1,   1,   1,   1,   1 )
++#define MPP2_SPI_SCK          MPP(  2, 0x2, 0, 0, 1,   1,   1,   1,   1 )
+ 
+ #define MPP3_GPO              MPP(  3, 0x0, 0, 1, 1,   1,   1,   1,   1 )
+-#define MPP3_NF_IO5           MPP(  3, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+-#define MPP3_SPI_MISO         MPP(  3, 0x2, 1, 0, 1,   1,   1,   1,   1 )
++#define MPP3_NF_IO5           MPP(  3, 0x1, 0, 0, 1,   1,   1,   1,   1 )
++#define MPP3_SPI_MISO         MPP(  3, 0x2, 0, 0, 1,   1,   1,   1,   1 )
+ 
+ #define MPP4_GPIO             MPP(  4, 0x0, 1, 1, 1,   1,   1,   1,   1 )
+-#define MPP4_NF_IO6           MPP(  4, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+-#define MPP4_UART0_RXD                MPP(  4, 0x2, 1, 0, 1,   1,   1,   1,   1 )
+-#define MPP4_SATA1_ACTn               MPP(  4, 0x5, 0, 1, 0,   0,   1,   1,   1 )
++#define MPP4_NF_IO6           MPP(  4, 0x1, 0, 0, 1,   1,   1,   1,   1 )
++#define MPP4_UART0_RXD                MPP(  4, 0x2, 0, 0, 1,   1,   1,   1,   1 )
++#define MPP4_SATA1_ACTn               MPP(  4, 0x5, 0, 0, 0,   0,   1,   1,   1 )
+ #define MPP4_LCD_VGA_HSYNC    MPP(  4, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+-#define MPP4_PTP_CLK          MPP(  4, 0xd, 1, 0, 1,   1,   1,   1,   0 )
++#define MPP4_PTP_CLK          MPP(  4, 0xd, 0, 0, 1,   1,   1,   1,   0 )
+ 
+ #define MPP5_GPO              MPP(  5, 0x0, 0, 1, 1,   1,   1,   1,   1 )
+-#define MPP5_NF_IO7           MPP(  5, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+-#define MPP5_UART0_TXD                MPP(  5, 0x2, 0, 1, 1,   1,   1,   1,   1 )
+-#define MPP5_PTP_TRIG_GEN     MPP(  5, 0x4, 0, 1, 1,   1,   1,   1,   0 )
+-#define MPP5_SATA0_ACTn               MPP(  5, 0x5, 0, 1, 0,   1,   1,   1,   1 )
++#define MPP5_NF_IO7           MPP(  5, 0x1, 0, 0, 1,   1,   1,   1,   1 )
++#define MPP5_UART0_TXD                MPP(  5, 0x2, 0, 0, 1,   1,   1,   1,   1 )
++#define MPP5_PTP_TRIG_GEN     MPP(  5, 0x4, 0, 0, 1,   1,   1,   1,   0 )
++#define MPP5_SATA0_ACTn               MPP(  5, 0x5, 0, 0, 0,   1,   1,   1,   1 )
+ #define MPP5_LCD_VGA_VSYNC    MPP(  5, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+ 
+-#define MPP6_SYSRST_OUTn      MPP(  6, 0x1, 0, 1, 1,   1,   1,   1,   1 )
+-#define MPP6_SPI_MOSI         MPP(  6, 0x2, 0, 1, 1,   1,   1,   1,   1 )
+-#define MPP6_PTP_TRIG_GEN     MPP(  6, 0x3, 0, 1, 1,   1,   1,   1,   0 )
++#define MPP6_SYSRST_OUTn      MPP(  6, 0x1, 0, 0, 1,   1,   1,   1,   1 )
++#define MPP6_SPI_MOSI         MPP(  6, 0x2, 0, 0, 1,   1,   1,   1,   1 )
++#define MPP6_PTP_TRIG_GEN     MPP(  6, 0x3, 0, 0, 1,   1,   1,   1,   0 )
+ 
+ #define MPP7_GPO              MPP(  7, 0x0, 0, 1, 1,   1,   1,   1,   1 )
+-#define MPP7_PEX_RST_OUTn     MPP(  7, 0x1, 0, 1, 1,   1,   1,   1,   0 )
+-#define MPP7_SPI_SCn          MPP(  7, 0x2, 0, 1, 1,   1,   1,   1,   1 )
+-#define MPP7_PTP_TRIG_GEN     MPP(  7, 0x3, 0, 1, 1,   1,   1,   1,   0 )
+-#define MPP7_LCD_PWM          MPP(  7, 0xb, 0, 1, 0,   0,   0,   0,   1 )
++#define MPP7_PEX_RST_OUTn     MPP(  7, 0x1, 0, 0, 1,   1,   1,   1,   0 )
++#define MPP7_SPI_SCn          MPP(  7, 0x2, 0, 0, 1,   1,   1,   1,   1 )
++#define MPP7_PTP_TRIG_GEN     MPP(  7, 0x3, 0, 0, 1,   1,   1,   1,   0 )
++#define MPP7_LCD_PWM          MPP(  7, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+ 
+ #define MPP8_GPIO             MPP(  8, 0x0, 1, 1, 1,   1,   1,   1,   1 )
+-#define MPP8_TW0_SDA          MPP(  8, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+-#define MPP8_UART0_RTS                MPP(  8, 0x2, 0, 1, 1,   1,   1,   1,   1 )
+-#define MPP8_UART1_RTS                MPP(  8, 0x3, 0, 1, 1,   1,   1,   1,   1 )
+-#define MPP8_MII0_RXERR               MPP(  8, 0x4, 1, 0, 0,   1,   1,   1,   1 )
+-#define MPP8_SATA1_PRESENTn   MPP(  8, 0x5, 0, 1, 0,   0,   1,   1,   1 )
+-#define MPP8_PTP_CLK          MPP(  8, 0xc, 1, 0, 1,   1,   1,   1,   0 )
+-#define MPP8_MII0_COL         MPP(  8, 0xd, 1, 0, 1,   1,   1,   1,   1 )
++#define MPP8_TW0_SDA          MPP(  8, 0x1, 0, 0, 1,   1,   1,   1,   1 )
++#define MPP8_UART0_RTS                MPP(  8, 0x2, 0, 0, 1,   1,   1,   1,   1 )
++#define MPP8_UART1_RTS                MPP(  8, 0x3, 0, 0, 1,   1,   1,   1,   1 )
++#define MPP8_MII0_RXERR               MPP(  8, 0x4, 0, 0, 0,   1,   1,   1,   1 )
++#define MPP8_SATA1_PRESENTn   MPP(  8, 0x5, 0, 0, 0,   0,   1,   1,   1 )
++#define MPP8_PTP_CLK          MPP(  8, 0xc, 0, 0, 1,   1,   1,   1,   0 )
++#define MPP8_MII0_COL         MPP(  8, 0xd, 0, 0, 1,   1,   1,   1,   1 )
+ 
+ #define MPP9_GPIO             MPP(  9, 0x0, 1, 1, 1,   1,   1,   1,   1 )
+-#define MPP9_TW0_SCK          MPP(  9, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+-#define MPP9_UART0_CTS                MPP(  9, 0x2, 1, 0, 1,   1,   1,   1,   1 )
+-#define MPP9_UART1_CTS                MPP(  9, 0x3, 1, 0, 1,   1,   1,   1,   1 )
+-#define MPP9_SATA0_PRESENTn   MPP(  9, 0x5, 0, 1, 0,   1,   1,   1,   1 )
+-#define MPP9_PTP_EVENT_REQ    MPP(  9, 0xc, 1, 0, 1,   1,   1,   1,   0 )
+-#define MPP9_MII0_CRS         MPP(  9, 0xd, 1, 0, 1,   1,   1,   1,   1 )
++#define MPP9_TW0_SCK          MPP(  9, 0x1, 0, 0, 1,   1,   1,   1,   1 )
++#define MPP9_UART0_CTS                MPP(  9, 0x2, 0, 0, 1,   1,   1,   1,   1 )
++#define MPP9_UART1_CTS                MPP(  9, 0x3, 0, 0, 1,   1,   1,   1,   1 )
++#define MPP9_SATA0_PRESENTn   MPP(  9, 0x5, 0, 0, 0,   1,   1,   1,   1 )
++#define MPP9_PTP_EVENT_REQ    MPP(  9, 0xc, 0, 0, 1,   1,   1,   1,   0 )
++#define MPP9_MII0_CRS         MPP(  9, 0xd, 0, 0, 1,   1,   1,   1,   1 )
+ 
+ #define MPP10_GPO             MPP( 10, 0x0, 0, 1, 1,   1,   1,   1,   1 )
+-#define MPP10_SPI_SCK         MPP( 10, 0x2, 0, 1, 1,   1,   1,   1,   1 )
+-#define MPP10_UART0_TXD               MPP( 10, 0X3, 0, 1, 1,   1,   1,   1,   1 )
+-#define MPP10_SATA1_ACTn      MPP( 10, 0x5, 0, 1, 0,   0,   1,   1,   1 )
+-#define MPP10_PTP_TRIG_GEN    MPP( 10, 0xc, 0, 1, 1,   1,   1,   1,   0 )
++#define MPP10_SPI_SCK         MPP( 10, 0x2, 0, 0, 1,   1,   1,   1,   1 )
++#define MPP10_UART0_TXD               MPP( 10, 0X3, 0, 0, 1,   1,   1,   1,   1 )
++#define MPP10_SATA1_ACTn      MPP( 10, 0x5, 0, 0, 0,   0,   1,   1,   1 )
++#define MPP10_PTP_TRIG_GEN    MPP( 10, 0xc, 0, 0, 1,   1,   1,   1,   0 )
+ 
+ #define MPP11_GPIO            MPP( 11, 0x0, 1, 1, 1,   1,   1,   1,   1 )
+-#define MPP11_SPI_MISO                MPP( 11, 0x2, 1, 0, 1,   1,   1,   1,   1 )
+-#define MPP11_UART0_RXD               MPP( 11, 0x3, 1, 0, 1,   1,   1,   1,   1 )
+-#define MPP11_PTP_EVENT_REQ   MPP( 11, 0x4, 1, 0, 1,   1,   1,   1,   0 )
+-#define MPP11_PTP_TRIG_GEN    MPP( 11, 0xc, 0, 1, 1,   1,   1,   1,   0 )
+-#define MPP11_PTP_CLK         MPP( 11, 0xd, 1, 0, 1,   1,   1,   1,   0 )
+-#define MPP11_SATA0_ACTn      MPP( 11, 0x5, 0, 1, 0,   1,   1,   1,   1 )
++#define MPP11_SPI_MISO                MPP( 11, 0x2, 0, 0, 1,   1,   1,   1,   1 )
++#define MPP11_UART0_RXD               MPP( 11, 0x3, 0, 0, 1,   1,   1,   1,   1 )
++#define MPP11_PTP_EVENT_REQ   MPP( 11, 0x4, 0, 0, 1,   1,   1,   1,   0 )
++#define MPP11_PTP_TRIG_GEN    MPP( 11, 0xc, 0, 0, 1,   1,   1,   1,   0 )
++#define MPP11_PTP_CLK         MPP( 11, 0xd, 0, 0, 1,   1,   1,   1,   0 )
++#define MPP11_SATA0_ACTn      MPP( 11, 0x5, 0, 0, 0,   1,   1,   1,   1 )
+ 
+ #define MPP12_GPO             MPP( 12, 0x0, 0, 1, 1,   1,   1,   1,   1 )
+-#define MPP12_SD_CLK          MPP( 12, 0x1, 0, 1, 1,   1,   1,   1,   1 )
+-#define MPP12_AU_SPDIF0               MPP( 12, 0xa, 0, 1, 0,   0,   0,   0,   1 )
+-#define MPP12_SPI_MOSI                MPP( 12, 0xb, 0, 1, 0,   0,   0,   0,   1 )
+-#define MPP12_TW1_SDA         MPP( 12, 0xd, 1, 0, 0,   0,   0,   0,   1 )
++#define MPP12_SD_CLK          MPP( 12, 0x1, 0, 0, 1,   1,   1,   1,   1 )
++#define MPP12_AU_SPDIF0               MPP( 12, 0xa, 0, 0, 0,   0,   0,   0,   1 )
++#define MPP12_SPI_MOSI                MPP( 12, 0xb, 0, 0, 0,   0,   0,   0,   1 )
++#define MPP12_TW1_SDA         MPP( 12, 0xd, 0, 0, 0,   0,   0,   0,   1 )
+ 
+ #define MPP13_GPIO            MPP( 13, 0x0, 1, 1, 1,   1,   1,   1,   1 )
+-#define MPP13_SD_CMD          MPP( 13, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+-#define MPP13_UART1_TXD               MPP( 13, 0x3, 0, 1, 1,   1,   1,   1,   1 )
+-#define MPP13_AU_SPDIFRMCLK   MPP( 13, 0xa, 0, 1, 0,   0,   0,   0,   1 )
+-#define MPP13_LCDPWM          MPP( 13, 0xb, 0, 1, 0,   0,   0,   0,   1 )
++#define MPP13_SD_CMD          MPP( 13, 0x1, 0, 0, 1,   1,   1,   1,   1 )
++#define MPP13_UART1_TXD               MPP( 13, 0x3, 0, 0, 1,   1,   1,   1,   1 )
++#define MPP13_AU_SPDIFRMCLK   MPP( 13, 0xa, 0, 0, 0,   0,   0,   0,   1 )
++#define MPP13_LCDPWM          MPP( 13, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+ 
+ #define MPP14_GPIO            MPP( 14, 0x0, 1, 1, 1,   1,   1,   1,   1 )
+-#define MPP14_SD_D0           MPP( 14, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+-#define MPP14_UART1_RXD               MPP( 14, 0x3, 1, 0, 1,   1,   1,   1,   1 )
+-#define MPP14_SATA1_PRESENTn  MPP( 14, 0x4, 0, 1, 0,   0,   1,   1,   1 )
+-#define MPP14_AU_SPDIFI               MPP( 14, 0xa, 1, 0, 0,   0,   0,   0,   1 )
+-#define MPP14_AU_I2SDI                MPP( 14, 0xb, 1, 0, 0,   0,   0,   0,   1 )
+-#define MPP14_MII0_COL                MPP( 14, 0xd, 1, 0, 1,   1,   1,   1,   1 )
++#define MPP14_SD_D0           MPP( 14, 0x1, 0, 0, 1,   1,   1,   1,   1 )
++#define MPP14_UART1_RXD               MPP( 14, 0x3, 0, 0, 1,   1,   1,   1,   1 )
++#define MPP14_SATA1_PRESENTn  MPP( 14, 0x4, 0, 0, 0,   0,   1,   1,   1 )
++#define MPP14_AU_SPDIFI               MPP( 14, 0xa, 0, 0, 0,   0,   0,   0,   1 )
++#define MPP14_AU_I2SDI                MPP( 14, 0xb, 0, 0, 0,   0,   0,   0,   1 )
++#define MPP14_MII0_COL                MPP( 14, 0xd, 0, 0, 1,   1,   1,   1,   1 )
+ 
+ #define MPP15_GPIO            MPP( 15, 0x0, 1, 1, 1,   1,   1,   1,   1 )
+-#define MPP15_SD_D1           MPP( 15, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+-#define MPP15_UART0_RTS               MPP( 15, 0x2, 0, 1, 1,   1,   1,   1,   1 )
+-#define MPP15_UART1_TXD               MPP( 15, 0x3, 0, 1, 1,   1,   1,   1,   1 )
+-#define MPP15_SATA0_ACTn      MPP( 15, 0x4, 0, 1, 0,   1,   1,   1,   1 )
+-#define MPP15_SPI_CSn         MPP( 15, 0xb, 0, 1, 0,   0,   0,   0,   1 )
++#define MPP15_SD_D1           MPP( 15, 0x1, 0, 0, 1,   1,   1,   1,   1 )
++#define MPP15_UART0_RTS               MPP( 15, 0x2, 0, 0, 1,   1,   1,   1,   1 )
++#define MPP15_UART1_TXD               MPP( 15, 0x3, 0, 0, 1,   1,   1,   1,   1 )
++#define MPP15_SATA0_ACTn      MPP( 15, 0x4, 0, 0, 0,   1,   1,   1,   1 )
++#define MPP15_SPI_CSn         MPP( 15, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+ 
+ #define MPP16_GPIO            MPP( 16, 0x0, 1, 1, 1,   1,   1,   1,   1 )
+-#define MPP16_SD_D2           MPP( 16, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+-#define MPP16_UART0_CTS               MPP( 16, 0x2, 1, 0, 1,   1,   1,   1,   1 )
+-#define MPP16_UART1_RXD               MPP( 16, 0x3, 1, 0, 1,   1,   1,   1,   1 )
+-#define MPP16_SATA1_ACTn      MPP( 16, 0x4, 0, 1, 0,   0,   1,   1,   1 )
+-#define MPP16_LCD_EXT_REF_CLK MPP( 16, 0xb, 1, 0, 0,   0,   0,   0,   1 )
+-#define MPP16_MII0_CRS                MPP( 16, 0xd, 1, 0, 1,   1,   1,   1,   1 )
++#define MPP16_SD_D2           MPP( 16, 0x1, 0, 0, 1,   1,   1,   1,   1 )
++#define MPP16_UART0_CTS               MPP( 16, 0x2, 0, 0, 1,   1,   1,   1,   1 )
++#define MPP16_UART1_RXD               MPP( 16, 0x3, 0, 0, 1,   1,   1,   1,   1 )
++#define MPP16_SATA1_ACTn      MPP( 16, 0x4, 0, 0, 0,   0,   1,   1,   1 )
++#define MPP16_LCD_EXT_REF_CLK MPP( 16, 0xb, 0, 0, 0,   0,   0,   0,   1 )
++#define MPP16_MII0_CRS                MPP( 16, 0xd, 0, 0, 1,   1,   1,   1,   1 )
+ 
+ #define MPP17_GPIO            MPP( 17, 0x0, 1, 1, 1,   1,   1,   1,   1 )
+-#define MPP17_SD_D3           MPP( 17, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+-#define MPP17_SATA0_PRESENTn  MPP( 17, 0x4, 0, 1, 0,   1,   1,   1,   1 )
+-#define MPP17_SATA1_ACTn      MPP( 17, 0xa, 0, 1, 0,   0,   0,   0,   1 )
+-#define MPP17_TW1_SCK         MPP( 17, 0xd, 1, 1, 0,   0,   0,   0,   1 )
++#define MPP17_SD_D3           MPP( 17, 0x1, 0, 0, 1,   1,   1,   1,   1 )
++#define MPP17_SATA0_PRESENTn  MPP( 17, 0x4, 0, 0, 0,   1,   1,   1,   1 )
++#define MPP17_SATA1_ACTn      MPP( 17, 0xa, 0, 0, 0,   0,   0,   0,   1 )
++#define MPP17_TW1_SCK         MPP( 17, 0xd, 0, 0, 0,   0,   0,   0,   1 )
+ 
+ #define MPP18_GPO             MPP( 18, 0x0, 0, 1, 1,   1,   1,   1,   1 )
+-#define MPP18_NF_IO0          MPP( 18, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+-#define MPP18_PEX0_CLKREQ     MPP( 18, 0x2, 0, 1, 0,   0,   0,   0,   1 )
++#define MPP18_NF_IO0          MPP( 18, 0x1, 0, 0, 1,   1,   1,   1,   1 )
++#define MPP18_PEX0_CLKREQ     MPP( 18, 0x2, 0, 0, 0,   0,   0,   0,   1 )
+ 
+ #define MPP19_GPO             MPP( 19, 0x0, 0, 1, 1,   1,   1,   1,   1 )
+-#define MPP19_NF_IO1          MPP( 19, 0x1, 1, 1, 1,   1,   1,   1,   1 )
++#define MPP19_NF_IO1          MPP( 19, 0x1, 0, 0, 1,   1,   1,   1,   1 )
+ 
+ #define MPP20_GPIO            MPP( 20, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+-#define MPP20_TSMP0           MPP( 20, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+-#define MPP20_TDM_CH0_TX_QL   MPP( 20, 0x2, 0, 1, 0,   0,   1,   1,   1 )
++#define MPP20_TSMP0           MPP( 20, 0x1, 0, 0, 0,   0,   1,   1,   1 )
++#define MPP20_TDM_CH0_TX_QL   MPP( 20, 0x2, 0, 0, 0,   0,   1,   1,   1 )
+ #define MPP20_GE1_TXD0                MPP( 20, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+-#define MPP20_AU_SPDIFI               MPP( 20, 0x4, 1, 0, 0,   0,   1,   1,   1 )
+-#define MPP20_SATA1_ACTn      MPP( 20, 0x5, 0, 1, 0,   0,   1,   1,   1 )
++#define MPP20_AU_SPDIFI               MPP( 20, 0x4, 0, 0, 0,   0,   1,   1,   1 )
++#define MPP20_SATA1_ACTn      MPP( 20, 0x5, 0, 0, 0,   0,   1,   1,   1 )
+ #define MPP20_LCD_D0          MPP( 20, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+ 
+ #define MPP21_GPIO            MPP( 21, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+-#define MPP21_TSMP1           MPP( 21, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+-#define MPP21_TDM_CH0_RX_QL   MPP( 21, 0x2, 0, 1, 0,   0,   1,   1,   1 )
++#define MPP21_TSMP1           MPP( 21, 0x1, 0, 0, 0,   0,   1,   1,   1 )
++#define MPP21_TDM_CH0_RX_QL   MPP( 21, 0x2, 0, 0, 0,   0,   1,   1,   1 )
+ #define MPP21_GE1_TXD1                MPP( 21, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+-#define MPP21_AU_SPDIFO               MPP( 21, 0x4, 0, 1, 0,   0,   1,   1,   1 )
+-#define MPP21_SATA0_ACTn      MPP( 21, 0x5, 0, 1, 0,   1,   1,   1,   1 )
++#define MPP21_AU_SPDIFO               MPP( 21, 0x4, 0, 0, 0,   0,   1,   1,   1 )
++#define MPP21_SATA0_ACTn      MPP( 21, 0x5, 0, 0, 0,   1,   1,   1,   1 )
+ #define MPP21_LCD_D1          MPP( 21, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+ 
+ #define MPP22_GPIO            MPP( 22, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+-#define MPP22_TSMP2           MPP( 22, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+-#define MPP22_TDM_CH2_TX_QL   MPP( 22, 0x2, 0, 1, 0,   0,   1,   1,   1 )
++#define MPP22_TSMP2           MPP( 22, 0x1, 0, 0, 0,   0,   1,   1,   1 )
++#define MPP22_TDM_CH2_TX_QL   MPP( 22, 0x2, 0, 0, 0,   0,   1,   1,   1 )
+ #define MPP22_GE1_TXD2                MPP( 22, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+-#define MPP22_AU_SPDIFRMKCLK  MPP( 22, 0x4, 0, 1, 0,   0,   1,   1,   1 )
+-#define MPP22_SATA1_PRESENTn  MPP( 22, 0x5, 0, 1, 0,   0,   1,   1,   1 )
++#define MPP22_AU_SPDIFRMKCLK  MPP( 22, 0x4, 0, 0, 0,   0,   1,   1,   1 )
++#define MPP22_SATA1_PRESENTn  MPP( 22, 0x5, 0, 0, 0,   0,   1,   1,   1 )
+ #define MPP22_LCD_D2          MPP( 22, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+ 
+ #define MPP23_GPIO            MPP( 23, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+-#define MPP23_TSMP3           MPP( 23, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+-#define MPP23_TDM_CH2_RX_QL   MPP( 23, 0x2, 1, 0, 0,   0,   1,   1,   1 )
++#define MPP23_TSMP3           MPP( 23, 0x1, 0, 0, 0,   0,   1,   1,   1 )
++#define MPP23_TDM_CH2_RX_QL   MPP( 23, 0x2, 0, 0, 0,   0,   1,   1,   1 )
+ #define MPP23_GE1_TXD3                MPP( 23, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+-#define MPP23_AU_I2SBCLK      MPP( 23, 0x4, 0, 1, 0,   0,   1,   1,   1 )
+-#define MPP23_SATA0_PRESENTn  MPP( 23, 0x5, 0, 1, 0,   1,   1,   1,   1 )
++#define MPP23_AU_I2SBCLK      MPP( 23, 0x4, 0, 0, 0,   0,   1,   1,   1 )
++#define MPP23_SATA0_PRESENTn  MPP( 23, 0x5, 0, 0, 0,   1,   1,   1,   1 )
+ #define MPP23_LCD_D3          MPP( 23, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+ 
+ #define MPP24_GPIO            MPP( 24, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+-#define MPP24_TSMP4           MPP( 24, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+-#define MPP24_TDM_SPI_CS0     MPP( 24, 0x2, 0, 1, 0,   0,   1,   1,   1 )
++#define MPP24_TSMP4           MPP( 24, 0x1, 0, 0, 0,   0,   1,   1,   1 )
++#define MPP24_TDM_SPI_CS0     MPP( 24, 0x2, 0, 0, 0,   0,   1,   1,   1 )
+ #define MPP24_GE1_RXD0                MPP( 24, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+-#define MPP24_AU_I2SDO                MPP( 24, 0x4, 0, 1, 0,   0,   1,   1,   1 )
++#define MPP24_AU_I2SDO                MPP( 24, 0x4, 0, 0, 0,   0,   1,   1,   1 )
+ #define MPP24_LCD_D4          MPP( 24, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+ 
+ #define MPP25_GPIO            MPP( 25, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+-#define MPP25_TSMP5           MPP( 25, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+-#define MPP25_TDM_SPI_SCK     MPP( 25, 0x2, 0, 1, 0,   0,   1,   1,   1 )
++#define MPP25_TSMP5           MPP( 25, 0x1, 0, 0, 0,   0,   1,   1,   1 )
++#define MPP25_TDM_SPI_SCK     MPP( 25, 0x2, 0, 0, 0,   0,   1,   1,   1 )
+ #define MPP25_GE1_RXD1                MPP( 25, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+-#define MPP25_AU_I2SLRCLK     MPP( 25, 0x4, 0, 1, 0,   0,   1,   1,   1 )
++#define MPP25_AU_I2SLRCLK     MPP( 25, 0x4, 0, 0, 0,   0,   1,   1,   1 )
+ #define MPP25_LCD_D5          MPP( 25, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+ 
+ #define MPP26_GPIO            MPP( 26, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+-#define MPP26_TSMP6           MPP( 26, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+-#define MPP26_TDM_SPI_MISO    MPP( 26, 0x2, 1, 0, 0,   0,   1,   1,   1 )
++#define MPP26_TSMP6           MPP( 26, 0x1, 0, 0, 0,   0,   1,   1,   1 )
++#define MPP26_TDM_SPI_MISO    MPP( 26, 0x2, 0, 0, 0,   0,   1,   1,   1 )
+ #define MPP26_GE1_RXD2                MPP( 26, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+-#define MPP26_AU_I2SMCLK      MPP( 26, 0x4, 0, 1, 0,   0,   1,   1,   1 )
++#define MPP26_AU_I2SMCLK      MPP( 26, 0x4, 0, 0, 0,   0,   1,   1,   1 )
+ #define MPP26_LCD_D6          MPP( 26, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+ 
+ #define MPP27_GPIO            MPP( 27, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+-#define MPP27_TSMP7           MPP( 27, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+-#define MPP27_TDM_SPI_MOSI    MPP( 27, 0x2, 0, 1, 0,   0,   1,   1,   1 )
++#define MPP27_TSMP7           MPP( 27, 0x1, 0, 0, 0,   0,   1,   1,   1 )
++#define MPP27_TDM_SPI_MOSI    MPP( 27, 0x2, 0, 0, 0,   0,   1,   1,   1 )
+ #define MPP27_GE1_RXD3                MPP( 27, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+-#define MPP27_AU_I2SDI                MPP( 27, 0x4, 1, 0, 0,   0,   1,   1,   1 )
++#define MPP27_AU_I2SDI                MPP( 27, 0x4, 0, 0, 0,   0,   1,   1,   1 )
+ #define MPP27_LCD_D7          MPP( 27, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+ 
+ #define MPP28_GPIO            MPP( 28, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+-#define MPP28_TSMP8           MPP( 28, 0x1, 1, 1, 0,   0,   1,   1,   1 )
++#define MPP28_TSMP8           MPP( 28, 0x1, 0, 0, 0,   0,   1,   1,   1 )
+ #define MPP28_TDM_CODEC_INTn  MPP( 28, 0x2, 0, 0, 0,   0,   1,   1,   1 )
+ #define MPP28_GE1_COL         MPP( 28, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+-#define MPP28_AU_EXTCLK               MPP( 28, 0x4, 1, 0, 0,   0,   1,   1,   1 )
++#define MPP28_AU_EXTCLK               MPP( 28, 0x4, 0, 0, 0,   0,   1,   1,   1 )
+ #define MPP28_LCD_D8          MPP( 28, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+ 
+ #define MPP29_GPIO            MPP( 29, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+-#define MPP29_TSMP9           MPP( 29, 0x1, 1, 1, 0,   0,   1,   1,   1 )
++#define MPP29_TSMP9           MPP( 29, 0x1, 0, 0, 0,   0,   1,   1,   1 )
+ #define MPP29_TDM_CODEC_RSTn  MPP( 29, 0x2, 0, 0, 0,   0,   1,   1,   1 )
+ #define MPP29_GE1_TCLK                MPP( 29, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+ #define MPP29_LCD_D9          MPP( 29, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+ 
+ #define MPP30_GPIO            MPP( 30, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+-#define MPP30_TSMP10          MPP( 30, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+-#define MPP30_TDM_PCLK                MPP( 30, 0x2, 1, 1, 0,   0,   1,   1,   1 )
++#define MPP30_TSMP10          MPP( 30, 0x1, 0, 0, 0,   0,   1,   1,   1 )
++#define MPP30_TDM_PCLK                MPP( 30, 0x2, 0, 0, 0,   0,   1,   1,   1 )
+ #define MPP30_GE1_RXCTL               MPP( 30, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+ #define MPP30_LCD_D10         MPP( 30, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+ 
+ #define MPP31_GPIO            MPP( 31, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+-#define MPP31_TSMP11          MPP( 31, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+-#define MPP31_TDM_FS          MPP( 31, 0x2, 1, 1, 0,   0,   1,   1,   1 )
++#define MPP31_TSMP11          MPP( 31, 0x1, 0, 0, 0,   0,   1,   1,   1 )
++#define MPP31_TDM_FS          MPP( 31, 0x2, 0, 0, 0,   0,   1,   1,   1 )
+ #define MPP31_GE1_RXCLK               MPP( 31, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+ #define MPP31_LCD_D11         MPP( 31, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+ 
+ #define MPP32_GPIO            MPP( 32, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+-#define MPP32_TSMP12          MPP( 32, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+-#define MPP32_TDM_DRX         MPP( 32, 0x2, 1, 0, 0,   0,   1,   1,   1 )
++#define MPP32_TSMP12          MPP( 32, 0x1, 0, 0, 0,   0,   1,   1,   1 )
++#define MPP32_TDM_DRX         MPP( 32, 0x2, 0, 0, 0,   0,   1,   1,   1 )
+ #define MPP32_GE1_TCLKOUT     MPP( 32, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+ #define MPP32_LCD_D12         MPP( 32, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+ 
+ #define MPP33_GPO             MPP( 33, 0x0, 0, 1, 0,   1,   1,   1,   1 )
+-#define MPP33_TDM_DTX         MPP( 33, 0x2, 0, 1, 0,   0,   1,   1,   1 )
++#define MPP33_TDM_DTX         MPP( 33, 0x2, 0, 0, 0,   0,   1,   1,   1 )
+ #define MPP33_GE1_TXCTL               MPP( 33, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+ #define MPP33_LCD_D13         MPP( 33, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+ 
+ #define MPP34_GPIO            MPP( 34, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+-#define MPP34_TDM_SPI_CS1     MPP( 34, 0x2, 0, 1, 0,   0,   1,   1,   1 )
++#define MPP34_TDM_SPI_CS1     MPP( 34, 0x2, 0, 0, 0,   0,   1,   1,   1 )
+ #define MPP34_GE1_TXEN                MPP( 34, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+-#define MPP34_SATA1_ACTn      MPP( 34, 0x5, 0, 1, 0,   0,   0,   1,   1 )
++#define MPP34_SATA1_ACTn      MPP( 34, 0x5, 0, 0, 0,   0,   0,   1,   1 )
+ #define MPP34_LCD_D14         MPP( 34, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+ 
+ #define MPP35_GPIO            MPP( 35, 0x0, 1, 1, 1,   1,   1,   1,   1 )
+-#define MPP35_TDM_CH0_TX_QL   MPP( 35, 0x2, 0, 1, 0,   0,   1,   1,   1 )
++#define MPP35_TDM_CH0_TX_QL   MPP( 35, 0x2, 0, 0, 0,   0,   1,   1,   1 )
+ #define MPP35_GE1_RXERR               MPP( 35, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+-#define MPP35_SATA0_ACTn      MPP( 35, 0x5, 0, 1, 0,   1,   1,   1,   1 )
++#define MPP35_SATA0_ACTn      MPP( 35, 0x5, 0, 0, 0,   1,   1,   1,   1 )
+ #define MPP35_LCD_D15         MPP( 22, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+-#define MPP35_MII0_RXERR      MPP( 35, 0xc, 1, 0, 1,   1,   1,   1,   1 )
++#define MPP35_MII0_RXERR      MPP( 35, 0xc, 0, 0, 1,   1,   1,   1,   1 )
+ 
+ #define MPP36_GPIO            MPP( 36, 0x0, 1, 1, 1,   0,   0,   1,   1 )
+-#define MPP36_TSMP0           MPP( 36, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+-#define MPP36_TDM_SPI_CS1     MPP( 36, 0x2, 0, 1, 0,   0,   0,   1,   1 )
+-#define MPP36_AU_SPDIFI               MPP( 36, 0x4, 1, 0, 1,   0,   0,   1,   1 )
+-#define MPP36_TW1_SDA         MPP( 36, 0xb, 1, 1, 0,   0,   0,   0,   1 )
++#define MPP36_TSMP0           MPP( 36, 0x1, 0, 0, 0,   0,   0,   1,   1 )
++#define MPP36_TDM_SPI_CS1     MPP( 36, 0x2, 0, 0, 0,   0,   0,   1,   1 )
++#define MPP36_AU_SPDIFI               MPP( 36, 0x4, 0, 0, 1,   0,   0,   1,   1 )
++#define MPP36_TW1_SDA         MPP( 36, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+ 
+ #define MPP37_GPIO            MPP( 37, 0x0, 1, 1, 1,   0,   0,   1,   1 )
+-#define MPP37_TSMP1           MPP( 37, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+-#define MPP37_TDM_CH2_TX_QL   MPP( 37, 0x2, 0, 1, 0,   0,   0,   1,   1 )
+-#define MPP37_AU_SPDIFO               MPP( 37, 0x4, 0, 1, 1,   0,   0,   1,   1 )
+-#define MPP37_TW1_SCK         MPP( 37, 0xb, 1, 1, 0,   0,   0,   0,   1 )
++#define MPP37_TSMP1           MPP( 37, 0x1, 0, 0, 0,   0,   0,   1,   1 )
++#define MPP37_TDM_CH2_TX_QL   MPP( 37, 0x2, 0, 0, 0,   0,   0,   1,   1 )
++#define MPP37_AU_SPDIFO               MPP( 37, 0x4, 0, 0, 1,   0,   0,   1,   1 )
++#define MPP37_TW1_SCK         MPP( 37, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+ 
+ #define MPP38_GPIO            MPP( 38, 0x0, 1, 1, 1,   0,   0,   1,   1 )
+-#define MPP38_TSMP2           MPP( 38, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+-#define MPP38_TDM_CH2_RX_QL   MPP( 38, 0x2, 0, 1, 0,   0,   0,   1,   1 )
+-#define MPP38_AU_SPDIFRMLCLK  MPP( 38, 0x4, 0, 1, 1,   0,   0,   1,   1 )
++#define MPP38_TSMP2           MPP( 38, 0x1, 0, 0, 0,   0,   0,   1,   1 )
++#define MPP38_TDM_CH2_RX_QL   MPP( 38, 0x2, 0, 0, 0,   0,   0,   1,   1 )
++#define MPP38_AU_SPDIFRMLCLK  MPP( 38, 0x4, 0, 0, 1,   0,   0,   1,   1 )
+ #define MPP38_LCD_D18         MPP( 38, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+ 
+ #define MPP39_GPIO            MPP( 39, 0x0, 1, 1, 1,   0,   0,   1,   1 )
+-#define MPP39_TSMP3           MPP( 39, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+-#define MPP39_TDM_SPI_CS0     MPP( 39, 0x2, 0, 1, 0,   0,   0,   1,   1 )
+-#define MPP39_AU_I2SBCLK      MPP( 39, 0x4, 0, 1, 1,   0,   0,   1,   1 )
++#define MPP39_TSMP3           MPP( 39, 0x1, 0, 0, 0,   0,   0,   1,   1 )
++#define MPP39_TDM_SPI_CS0     MPP( 39, 0x2, 0, 0, 0,   0,   0,   1,   1 )
++#define MPP39_AU_I2SBCLK      MPP( 39, 0x4, 0, 0, 1,   0,   0,   1,   1 )
+ #define MPP39_LCD_D19         MPP( 39, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+ 
+ #define MPP40_GPIO            MPP( 40, 0x0, 1, 1, 1,   0,   0,   1,   1 )
+-#define MPP40_TSMP4           MPP( 40, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+-#define MPP40_TDM_SPI_SCK     MPP( 40, 0x2, 0, 1, 0,   0,   0,   1,   1 )
+-#define MPP40_AU_I2SDO                MPP( 40, 0x4, 0, 1, 1,   0,   0,   1,   1 )
++#define MPP40_TSMP4           MPP( 40, 0x1, 0, 0, 0,   0,   0,   1,   1 )
++#define MPP40_TDM_SPI_SCK     MPP( 40, 0x2, 0, 0, 0,   0,   0,   1,   1 )
++#define MPP40_AU_I2SDO                MPP( 40, 0x4, 0, 0, 1,   0,   0,   1,   1 )
+ #define MPP40_LCD_D20         MPP( 40, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+ 
+ #define MPP41_GPIO            MPP( 41, 0x0, 1, 1, 1,   0,   0,   1,   1 )
+-#define MPP41_TSMP5           MPP( 41, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+-#define MPP41_TDM_SPI_MISO    MPP( 41, 0x2, 1, 0, 0,   0,   0,   1,   1 )
+-#define MPP41_AU_I2SLRCLK     MPP( 41, 0x4, 0, 1, 1,   0,   0,   1,   1 )
++#define MPP41_TSMP5           MPP( 41, 0x1, 0, 0, 0,   0,   0,   1,   1 )
++#define MPP41_TDM_SPI_MISO    MPP( 41, 0x2, 0, 0, 0,   0,   0,   1,   1 )
++#define MPP41_AU_I2SLRCLK     MPP( 41, 0x4, 0, 0, 1,   0,   0,   1,   1 )
+ #define MPP41_LCD_D21         MPP( 41, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+ 
+ #define MPP42_GPIO            MPP( 42, 0x0, 1, 1, 1,   0,   0,   1,   1 )
+-#define MPP42_TSMP6           MPP( 42, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+-#define MPP42_TDM_SPI_MOSI    MPP( 42, 0x2, 0, 1, 0,   0,   0,   1,   1 )
+-#define MPP42_AU_I2SMCLK      MPP( 42, 0x4, 0, 1, 1,   0,   0,   1,   1 )
++#define MPP42_TSMP6           MPP( 42, 0x1, 0, 0, 0,   0,   0,   1,   1 )
++#define MPP42_TDM_SPI_MOSI    MPP( 42, 0x2, 0, 0, 0,   0,   0,   1,   1 )
++#define MPP42_AU_I2SMCLK      MPP( 42, 0x4, 0, 0, 1,   0,   0,   1,   1 )
+ #define MPP42_LCD_D22         MPP( 42, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+ 
+ #define MPP43_GPIO            MPP( 43, 0x0, 1, 1, 1,   0,   0,   1,   1 )
+-#define MPP43_TSMP7           MPP( 43, 0x1, 1, 1, 0,   0,   0,   1,   1 )
++#define MPP43_TSMP7           MPP( 43, 0x1, 0, 0, 0,   0,   0,   1,   1 )
+ #define MPP43_TDM_CODEC_INTn  MPP( 43, 0x2, 0, 0, 0,   0,   0,   1,   1 )
+-#define MPP43_AU_I2SDI                MPP( 43, 0x4, 1, 0, 1,   0,   0,   1,   1 )
++#define MPP43_AU_I2SDI                MPP( 43, 0x4, 0, 0, 1,   0,   0,   1,   1 )
+ #define MPP43_LCD_D23         MPP( 22, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+ 
+ #define MPP44_GPIO            MPP( 44, 0x0, 1, 1, 1,   0,   0,   1,   1 )
+-#define MPP44_TSMP8           MPP( 44, 0x1, 1, 1, 0,   0,   0,   1,   1 )
++#define MPP44_TSMP8           MPP( 44, 0x1, 0, 0, 0,   0,   0,   1,   1 )
+ #define MPP44_TDM_CODEC_RSTn  MPP( 44, 0x2, 0, 0, 0,   0,   0,   1,   1 )
+-#define MPP44_AU_EXTCLK               MPP( 44, 0x4, 1, 0, 1,   0,   0,   1,   1 )
++#define MPP44_AU_EXTCLK               MPP( 44, 0x4, 0, 0, 1,   0,   0,   1,   1 )
+ #define MPP44_LCD_CLK         MPP( 44, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+ 
+ #define MPP45_GPIO            MPP( 45, 0x0, 1, 1, 0,   0,   0,   1,   1 )
+-#define MPP45_TSMP9           MPP( 45, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+-#define MPP45_TDM_PCLK                MPP( 45, 0x2, 1, 1, 0,   0,   0,   1,   1 )
++#define MPP45_TSMP9           MPP( 45, 0x1, 0, 0, 0,   0,   0,   1,   1 )
++#define MPP45_TDM_PCLK                MPP( 45, 0x2, 0, 0, 0,   0,   0,   1,   1 )
+ #define MPP245_LCD_E          MPP( 45, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+ 
+ #define MPP46_GPIO            MPP( 46, 0x0, 1, 1, 0,   0,   0,   1,   1 )
+-#define MPP46_TSMP10          MPP( 46, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+-#define MPP46_TDM_FS          MPP( 46, 0x2, 1, 1, 0,   0,   0,   1,   1 )
++#define MPP46_TSMP10          MPP( 46, 0x1, 0, 0, 0,   0,   0,   1,   1 )
++#define MPP46_TDM_FS          MPP( 46, 0x2, 0, 0, 0,   0,   0,   1,   1 )
+ #define MPP46_LCD_HSYNC               MPP( 46, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+ 
+ #define MPP47_GPIO            MPP( 47, 0x0, 1, 1, 0,   0,   0,   1,   1 )
+-#define MPP47_TSMP11          MPP( 47, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+-#define MPP47_TDM_DRX         MPP( 47, 0x2, 1, 0, 0,   0,   0,   1,   1 )
++#define MPP47_TSMP11          MPP( 47, 0x1, 0, 0, 0,   0,   0,   1,   1 )
++#define MPP47_TDM_DRX         MPP( 47, 0x2, 0, 0, 0,   0,   0,   1,   1 )
+ #define MPP47_LCD_VSYNC               MPP( 47, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+ 
+ #define MPP48_GPIO            MPP( 48, 0x0, 1, 1, 0,   0,   0,   1,   1 )
+-#define MPP48_TSMP12          MPP( 48, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+-#define MPP48_TDM_DTX         MPP( 48, 0x2, 0, 1, 0,   0,   0,   1,   1 )
++#define MPP48_TSMP12          MPP( 48, 0x1, 0, 0, 0,   0,   0,   1,   1 )
++#define MPP48_TDM_DTX         MPP( 48, 0x2, 0, 0, 0,   0,   0,   1,   1 )
+ #define MPP48_LCD_D16         MPP( 22, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+ 
+ #define MPP49_GPIO            MPP( 49, 0x0, 1, 1, 0,   0,   0,   1,   0 )
+ #define MPP49_GPO             MPP( 49, 0x0, 0, 1, 0,   0,   0,   0,   1 )
+-#define MPP49_TSMP9           MPP( 49, 0x1, 1, 1, 0,   0,   0,   1,   0 )
+-#define MPP49_TDM_CH0_RX_QL   MPP( 49, 0x2, 0, 1, 0,   0,   0,   1,   1 )
+-#define MPP49_PTP_CLK         MPP( 49, 0x5, 1, 0, 0,   0,   0,   1,   0 )
+-#define MPP49_PEX0_CLKREQ     MPP( 49, 0xa, 0, 1, 0,   0,   0,   0,   1 )
++#define MPP49_TSMP9           MPP( 49, 0x1, 0, 0, 0,   0,   0,   1,   0 )
++#define MPP49_TDM_CH0_RX_QL   MPP( 49, 0x2, 0, 0, 0,   0,   0,   1,   1 )
++#define MPP49_PTP_CLK         MPP( 49, 0x5, 0, 0, 0,   0,   0,   1,   0 )
++#define MPP49_PEX0_CLKREQ     MPP( 49, 0xa, 0, 0, 0,   0,   0,   0,   1 )
+ #define MPP49_LCD_D17         MPP( 49, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+ 
+ #define MPP_MAX                       49
+--- a/arch/arm/mach-mv78xx0/mpp.h
++++ b/arch/arm/mach-mv78xx0/mpp.h
+@@ -24,296 +24,296 @@
+ #define MPP_78100_A0_MASK    MPP(0, 0x0, 0, 0, 1)
+ 
+ #define MPP0_GPIO        MPP(0, 0x0, 1, 1, 1)
+-#define MPP0_GE0_COL        MPP(0, 0x1, 1, 0, 1)
+-#define MPP0_GE1_TXCLK        MPP(0, 0x2, 0, 1, 1)
++#define MPP0_GE0_COL        MPP(0, 0x1, 0, 0, 1)
++#define MPP0_GE1_TXCLK        MPP(0, 0x2, 0, 0, 1)
+ #define MPP0_UNUSED        MPP(0, 0x3, 0, 0, 1)
+ 
+ #define MPP1_GPIO        MPP(1, 0x0, 1, 1, 1)
+-#define MPP1_GE0_RXERR        MPP(1, 0x1, 1, 0, 1)
+-#define MPP1_GE1_TXCTL        MPP(1, 0x2, 0, 1, 1)
++#define MPP1_GE0_RXERR        MPP(1, 0x1, 0, 0, 1)
++#define MPP1_GE1_TXCTL        MPP(1, 0x2, 0, 0, 1)
+ #define MPP1_UNUSED        MPP(1, 0x3, 0, 0, 1)
+ 
+ #define MPP2_GPIO        MPP(2, 0x0, 1, 1, 1)
+-#define MPP2_GE0_CRS        MPP(2, 0x1, 1, 0, 1)
+-#define MPP2_GE1_RXCTL        MPP(2, 0x2, 1, 0, 1)
++#define MPP2_GE0_CRS        MPP(2, 0x1, 0, 0, 1)
++#define MPP2_GE1_RXCTL        MPP(2, 0x2, 0, 0, 1)
+ #define MPP2_UNUSED        MPP(2, 0x3, 0, 0, 1)
+ 
+ #define MPP3_GPIO        MPP(3, 0x0, 1, 1, 1)
+-#define MPP3_GE0_TXERR        MPP(3, 0x1, 0, 1, 1)
+-#define MPP3_GE1_RXCLK        MPP(3, 0x2, 1, 0, 1)
++#define MPP3_GE0_TXERR        MPP(3, 0x1, 0, 0, 1)
++#define MPP3_GE1_RXCLK        MPP(3, 0x2, 0, 0, 1)
+ #define MPP3_UNUSED        MPP(3, 0x3, 0, 0, 1)
+ 
+ #define MPP4_GPIO        MPP(4, 0x0, 1, 1, 1)
+-#define MPP4_GE0_TXD4        MPP(4, 0x1, 0, 1, 1)
+-#define MPP4_GE1_TXD0        MPP(4, 0x2, 0, 1, 1)
++#define MPP4_GE0_TXD4        MPP(4, 0x1, 0, 0, 1)
++#define MPP4_GE1_TXD0        MPP(4, 0x2, 0, 0, 1)
+ #define MPP4_UNUSED        MPP(4, 0x3, 0, 0, 1)
+ 
+ #define MPP5_GPIO        MPP(5, 0x0, 1, 1, 1)
+-#define MPP5_GE0_TXD5        MPP(5, 0x1, 0, 1, 1)
+-#define MPP5_GE1_TXD1        MPP(5, 0x2, 0, 1, 1)
++#define MPP5_GE0_TXD5        MPP(5, 0x1, 0, 0, 1)
++#define MPP5_GE1_TXD1        MPP(5, 0x2, 0, 0, 1)
+ #define MPP5_UNUSED        MPP(5, 0x3, 0, 0, 1)
+ 
+ #define MPP6_GPIO        MPP(6, 0x0, 1, 1, 1)
+-#define MPP6_GE0_TXD6        MPP(6, 0x1, 0, 1, 1)
+-#define MPP6_GE1_TXD2        MPP(6, 0x2, 0, 1, 1)
++#define MPP6_GE0_TXD6        MPP(6, 0x1, 0, 0, 1)
++#define MPP6_GE1_TXD2        MPP(6, 0x2, 0, 0, 1)
+ #define MPP6_UNUSED        MPP(6, 0x3, 0, 0, 1)
+ 
+ #define MPP7_GPIO        MPP(7, 0x0, 1, 1, 1)
+-#define MPP7_GE0_TXD7        MPP(7, 0x1, 0, 1, 1)
+-#define MPP7_GE1_TXD3        MPP(7, 0x2, 0, 1, 1)
++#define MPP7_GE0_TXD7        MPP(7, 0x1, 0, 0, 1)
++#define MPP7_GE1_TXD3        MPP(7, 0x2, 0, 0, 1)
+ #define MPP7_UNUSED        MPP(7, 0x3, 0, 0, 1)
+ 
+ #define MPP8_GPIO        MPP(8, 0x0, 1, 1, 1)
+-#define MPP8_GE0_RXD4        MPP(8, 0x1, 1, 0, 1)
+-#define MPP8_GE1_RXD0        MPP(8, 0x2, 1, 0, 1)
++#define MPP8_GE0_RXD4        MPP(8, 0x1, 0, 0, 1)
++#define MPP8_GE1_RXD0        MPP(8, 0x2, 0, 0, 1)
+ #define MPP8_UNUSED        MPP(8, 0x3, 0, 0, 1)
+ 
+ #define MPP9_GPIO        MPP(9, 0x0, 1, 1, 1)
+-#define MPP9_GE0_RXD5        MPP(9, 0x1, 1, 0, 1)
+-#define MPP9_GE1_RXD1        MPP(9, 0x2, 1, 0, 1)
++#define MPP9_GE0_RXD5        MPP(9, 0x1, 0, 0, 1)
++#define MPP9_GE1_RXD1        MPP(9, 0x2, 0, 0, 1)
+ #define MPP9_UNUSED        MPP(9, 0x3, 0, 0, 1)
+ 
+ #define MPP10_GPIO        MPP(10, 0x0, 1, 1, 1)
+-#define MPP10_GE0_RXD6        MPP(10, 0x1, 1, 0, 1)
+-#define MPP10_GE1_RXD2        MPP(10, 0x2, 1, 0, 1)
++#define MPP10_GE0_RXD6        MPP(10, 0x1, 0, 0, 1)
++#define MPP10_GE1_RXD2        MPP(10, 0x2, 0, 0, 1)
+ #define MPP10_UNUSED        MPP(10, 0x3, 0, 0, 1)
+ 
+ #define MPP11_GPIO        MPP(11, 0x0, 1, 1, 1)
+-#define MPP11_GE0_RXD7        MPP(11, 0x1, 1, 0, 1)
+-#define MPP11_GE1_RXD3        MPP(11, 0x2, 1, 0, 1)
++#define MPP11_GE0_RXD7        MPP(11, 0x1, 0, 0, 1)
++#define MPP11_GE1_RXD3        MPP(11, 0x2, 0, 0, 1)
+ #define MPP11_UNUSED        MPP(11, 0x3, 0, 0, 1)
+ 
+ #define MPP12_GPIO        MPP(12, 0x0, 1, 1, 1)
+-#define MPP12_M_BB        MPP(12, 0x3, 1, 0, 1)
+-#define MPP12_UA0_CTSn        MPP(12, 0x4, 1, 0, 1)
+-#define MPP12_NAND_FLASH_REn0    MPP(12, 0x5, 0, 1, 1)
+-#define MPP12_TDM0_SCSn        MPP(12, 0X6, 0, 1, 1)
++#define MPP12_M_BB        MPP(12, 0x3, 0, 0, 1)
++#define MPP12_UA0_CTSn        MPP(12, 0x4, 0, 0, 1)
++#define MPP12_NAND_FLASH_REn0    MPP(12, 0x5, 0, 0, 1)
++#define MPP12_TDM0_SCSn        MPP(12, 0X6, 0, 0, 1)
+ #define MPP12_UNUSED        MPP(12, 0x1, 0, 0, 1)
+ 
+ #define MPP13_GPIO        MPP(13, 0x0, 1, 1, 1)
+-#define MPP13_SYSRST_OUTn    MPP(13, 0x3, 0, 1, 1)
+-#define MPP13_UA0_RTSn        MPP(13, 0x4, 0, 1, 1)
+-#define MPP13_NAN_FLASH_WEn0    MPP(13, 0x5, 0, 1, 1)
+-#define MPP13_TDM_SCLK        MPP(13, 0x6, 0, 1, 1)
++#define MPP13_SYSRST_OUTn    MPP(13, 0x3, 0, 0, 1)
++#define MPP13_UA0_RTSn        MPP(13, 0x4, 0, 0, 1)
++#define MPP13_NAN_FLASH_WEn0    MPP(13, 0x5, 0, 0, 1)
++#define MPP13_TDM_SCLK        MPP(13, 0x6, 0, 0, 1)
+ #define MPP13_UNUSED        MPP(13, 0x1, 0, 0, 1)
+ 
+ #define MPP14_GPIO        MPP(14, 0x0, 1, 1, 1)
+-#define MPP14_SATA1_ACTn    MPP(14, 0x3, 0, 1, 1)
+-#define MPP14_UA1_CTSn        MPP(14, 0x4, 1, 0, 1)
+-#define MPP14_NAND_FLASH_REn1    MPP(14, 0x5, 0, 1, 1)
+-#define MPP14_TDM_SMOSI        MPP(14, 0x6, 0, 1, 1)
++#define MPP14_SATA1_ACTn    MPP(14, 0x3, 0, 0, 1)
++#define MPP14_UA1_CTSn        MPP(14, 0x4, 0, 0, 1)
++#define MPP14_NAND_FLASH_REn1    MPP(14, 0x5, 0, 0, 1)
++#define MPP14_TDM_SMOSI        MPP(14, 0x6, 0, 0, 1)
+ #define MPP14_UNUSED        MPP(14, 0x1, 0, 0, 1)
+ 
+ #define MPP15_GPIO        MPP(15, 0x0, 1, 1, 1)
+-#define MPP15_SATA0_ACTn    MPP(15, 0x3, 0, 1, 1)
+-#define MPP15_UA1_RTSn        MPP(15, 0x4, 0, 1, 1)
+-#define MPP15_NAND_FLASH_WEn1    MPP(15, 0x5, 0, 1, 1)
+-#define MPP15_TDM_SMISO        MPP(15, 0x6, 1, 0, 1)
++#define MPP15_SATA0_ACTn    MPP(15, 0x3, 0, 0, 1)
++#define MPP15_UA1_RTSn        MPP(15, 0x4, 0, 0, 1)
++#define MPP15_NAND_FLASH_WEn1    MPP(15, 0x5, 0, 0, 1)
++#define MPP15_TDM_SMISO        MPP(15, 0x6, 0, 0, 1)
+ #define MPP15_UNUSED        MPP(15, 0x1, 0, 0, 1)
+ 
+ #define MPP16_GPIO        MPP(16, 0x0, 1, 1, 1)
+-#define MPP16_SATA1_PRESENTn    MPP(16, 0x3, 0, 1, 1)
+-#define MPP16_UA2_TXD        MPP(16, 0x4, 0, 1, 1)
+-#define MPP16_NAND_FLASH_REn3    MPP(16, 0x5, 0, 1, 1)
+-#define MPP16_TDM_INTn        MPP(16, 0x6, 1, 0, 1)
++#define MPP16_SATA1_PRESENTn    MPP(16, 0x3, 0, 0, 1)
++#define MPP16_UA2_TXD        MPP(16, 0x4, 0, 0, 1)
++#define MPP16_NAND_FLASH_REn3    MPP(16, 0x5, 0, 0, 1)
++#define MPP16_TDM_INTn        MPP(16, 0x6, 0, 0, 1)
+ #define MPP16_UNUSED        MPP(16, 0x1, 0, 0, 1)
+ 
+ 
+ #define MPP17_GPIO        MPP(17, 0x0, 1, 1, 1)
+-#define MPP17_SATA0_PRESENTn    MPP(17, 0x3, 0, 1, 1)
+-#define MPP17_UA2_RXD        MPP(17, 0x4, 1, 0, 1)
+-#define MPP17_NAND_FLASH_WEn3    MPP(17, 0x5, 0, 1, 1)
+-#define MPP17_TDM_RSTn        MPP(17, 0x6, 0, 1, 1)
++#define MPP17_SATA0_PRESENTn    MPP(17, 0x3, 0, 0, 1)
++#define MPP17_UA2_RXD        MPP(17, 0x4, 0, 0, 1)
++#define MPP17_NAND_FLASH_WEn3    MPP(17, 0x5, 0, 0, 1)
++#define MPP17_TDM_RSTn        MPP(17, 0x6, 0, 0, 1)
+ #define MPP17_UNUSED        MPP(17, 0x1, 0, 0, 1)
+ 
+ 
+ #define MPP18_GPIO        MPP(18, 0x0, 1, 1, 1)
+-#define MPP18_UA0_CTSn        MPP(18, 0x4, 1, 0, 1)
+-#define MPP18_BOOT_FLASH_REn    MPP(18, 0x5, 0, 1, 1)
++#define MPP18_UA0_CTSn        MPP(18, 0x4, 0, 0, 1)
++#define MPP18_BOOT_FLASH_REn    MPP(18, 0x5, 0, 0, 1)
+ #define MPP18_UNUSED        MPP(18, 0x1, 0, 0, 1)
+ 
+ 
+ 
+ #define MPP19_GPIO        MPP(19, 0x0, 1, 1, 1)
+-#define MPP19_UA0_CTSn        MPP(19, 0x4, 0, 1, 1)
+-#define MPP19_BOOT_FLASH_WEn    MPP(19, 0x5, 0, 1, 1)
++#define MPP19_UA0_CTSn        MPP(19, 0x4, 0, 0, 1)
++#define MPP19_BOOT_FLASH_WEn    MPP(19, 0x5, 0, 0, 1)
+ #define MPP19_UNUSED        MPP(19, 0x1, 0, 0, 1)
+ 
+ 
+ #define MPP20_GPIO        MPP(20, 0x0, 1, 1, 1)
+-#define MPP20_UA1_CTSs        MPP(20, 0x4, 1, 0, 1)
+-#define MPP20_TDM_PCLK        MPP(20, 0x6, 1, 1, 0)
++#define MPP20_UA1_CTSs        MPP(20, 0x4, 0, 0, 1)
++#define MPP20_TDM_PCLK        MPP(20, 0x6, 0, 0, 0)
+ #define MPP20_UNUSED        MPP(20, 0x1, 0, 0, 1)
+ 
+ 
+ 
+ #define MPP21_GPIO        MPP(21, 0x0, 1, 1, 1)
+-#define MPP21_UA1_CTSs        MPP(21, 0x4, 0, 1, 1)
+-#define MPP21_TDM_FSYNC        MPP(21, 0x6, 1, 1, 0)
++#define MPP21_UA1_CTSs        MPP(21, 0x4, 0, 0, 1)
++#define MPP21_TDM_FSYNC        MPP(21, 0x6, 0, 0, 0)
+ #define MPP21_UNUSED        MPP(21, 0x1, 0, 0, 1)
+ 
+ 
+ 
+ #define MPP22_GPIO        MPP(22, 0x0, 1, 1, 1)
+-#define MPP22_UA3_TDX        MPP(22, 0x4, 0, 1, 1)
+-#define MPP22_NAND_FLASH_REn2    MPP(22, 0x5, 0, 1, 1)
+-#define MPP22_TDM_DRX        MPP(22, 0x6, 1, 0, 1)
++#define MPP22_UA3_TDX        MPP(22, 0x4, 0, 0, 1)
++#define MPP22_NAND_FLASH_REn2    MPP(22, 0x5, 0, 0, 1)
++#define MPP22_TDM_DRX        MPP(22, 0x6, 0, 0, 1)
+ #define MPP22_UNUSED        MPP(22, 0x1, 0, 0, 1)
+ 
+ 
+ 
+ #define MPP23_GPIO        MPP(23, 0x0, 1, 1, 1)
+-#define MPP23_UA3_RDX        MPP(23, 0x4, 1, 0, 1)
+-#define MPP23_NAND_FLASH_WEn2    MPP(23, 0x5, 0, 1, 1)
+-#define MPP23_TDM_DTX        MPP(23, 0x6, 0, 1, 1)
++#define MPP23_UA3_RDX        MPP(23, 0x4, 0, 0, 1)
++#define MPP23_NAND_FLASH_WEn2    MPP(23, 0x5, 0, 0, 1)
++#define MPP23_TDM_DTX        MPP(23, 0x6, 0, 0, 1)
+ #define MPP23_UNUSED        MPP(23, 0x1, 0, 0, 1)
+ 
+ 
+ #define MPP24_GPIO        MPP(24, 0x0, 1, 1, 1)
+-#define MPP24_UA2_TXD        MPP(24, 0x4, 0, 1, 1)
+-#define MPP24_TDM_INTn        MPP(24, 0x6, 1, 0, 1)
++#define MPP24_UA2_TXD        MPP(24, 0x4, 0, 0, 1)
++#define MPP24_TDM_INTn        MPP(24, 0x6, 0, 0, 1)
+ #define MPP24_UNUSED        MPP(24, 0x1, 0, 0, 1)
+ 
+ 
+ #define MPP25_GPIO        MPP(25, 0x0, 1, 1, 1)
+-#define MPP25_UA2_RXD        MPP(25, 0x4, 1, 0, 1)
+-#define MPP25_TDM_RSTn        MPP(25, 0x6, 0, 1, 1)
++#define MPP25_UA2_RXD        MPP(25, 0x4, 0, 0, 1)
++#define MPP25_TDM_RSTn        MPP(25, 0x6, 0, 0, 1)
+ #define MPP25_UNUSED        MPP(25, 0x1, 0, 0, 1)
+ 
+ 
+ #define MPP26_GPIO        MPP(26, 0x0, 1, 1, 1)
+-#define MPP26_UA2_CTSn        MPP(26, 0x4, 1, 0, 1)
+-#define MPP26_TDM_PCLK        MPP(26, 0x6, 1, 1, 1)
++#define MPP26_UA2_CTSn        MPP(26, 0x4, 0, 0, 1)
++#define MPP26_TDM_PCLK        MPP(26, 0x6, 0, 0, 1)
+ #define MPP26_UNUSED        MPP(26, 0x1, 0, 0, 1)
+ 
+ 
+ #define MPP27_GPIO        MPP(27, 0x0, 1, 1, 1)
+-#define MPP27_UA2_RTSn        MPP(27, 0x4, 0, 1, 1)
+-#define MPP27_TDM_FSYNC        MPP(27, 0x6, 1, 1, 1)
++#define MPP27_UA2_RTSn        MPP(27, 0x4, 0, 0, 1)
++#define MPP27_TDM_FSYNC        MPP(27, 0x6, 0, 0, 1)
+ #define MPP27_UNUSED        MPP(27, 0x1, 0, 0, 1)
+ 
+ 
+ #define MPP28_GPIO        MPP(28, 0x0, 1, 1, 1)
+-#define MPP28_UA3_TXD        MPP(28, 0x4, 0, 1, 1)
+-#define MPP28_TDM_DRX        MPP(28, 0x6, 1, 0, 1)
++#define MPP28_UA3_TXD        MPP(28, 0x4, 0, 0, 1)
++#define MPP28_TDM_DRX        MPP(28, 0x6, 0, 0, 1)
+ #define MPP28_UNUSED        MPP(28, 0x1, 0, 0, 1)
+ 
+ #define MPP29_GPIO        MPP(29, 0x0, 1, 1, 1)
+-#define MPP29_UA3_RXD        MPP(29, 0x4, 1, 0, 1)
+-#define MPP29_SYSRST_OUTn    MPP(29, 0x5, 0, 1, 1)
+-#define MPP29_TDM_DTX        MPP(29, 0x6, 0, 1, 1)
++#define MPP29_UA3_RXD        MPP(29, 0x4, 0, 0, 1)
++#define MPP29_SYSRST_OUTn    MPP(29, 0x5, 0, 0, 1)
++#define MPP29_TDM_DTX        MPP(29, 0x6, 0, 0, 1)
+ #define MPP29_UNUSED        MPP(29, 0x1, 0, 0, 1)
+ 
+ #define MPP30_GPIO        MPP(30, 0x0, 1, 1, 1)
+-#define MPP30_UA3_CTSn        MPP(30, 0x4, 1, 0, 1)
++#define MPP30_UA3_CTSn        MPP(30, 0x4, 0, 0, 1)
+ #define MPP30_UNUSED        MPP(30, 0x1, 0, 0, 1)
+ 
+ #define MPP31_GPIO        MPP(31, 0x0, 1, 1, 1)
+-#define MPP31_UA3_RTSn        MPP(31, 0x4, 0, 1, 1)
+-#define MPP31_TDM1_SCSn        MPP(31, 0x6, 0, 1, 1)
++#define MPP31_UA3_RTSn        MPP(31, 0x4, 0, 0, 1)
++#define MPP31_TDM1_SCSn        MPP(31, 0x6, 0, 0, 1)
+ #define MPP31_UNUSED        MPP(31, 0x1, 0, 0, 1)
+ 
+ 
+ #define MPP32_GPIO        MPP(32, 0x1, 1, 1, 1)
+-#define MPP32_UA3_TDX        MPP(32, 0x4, 0, 1, 1)
+-#define MPP32_SYSRST_OUTn    MPP(32, 0x5, 0, 1, 1)
+-#define MPP32_TDM0_RXQ        MPP(32, 0x6, 0, 1, 1)
++#define MPP32_UA3_TDX        MPP(32, 0x4, 0, 0, 1)
++#define MPP32_SYSRST_OUTn    MPP(32, 0x5, 0, 0, 1)
++#define MPP32_TDM0_RXQ        MPP(32, 0x6, 0, 0, 1)
+ #define MPP32_UNUSED        MPP(32, 0x3, 0, 0, 1)
+ 
+ 
+ #define MPP33_GPIO        MPP(33, 0x1, 1, 1, 1)
+-#define MPP33_UA3_RDX        MPP(33, 0x4, 1, 0, 1)
+-#define MPP33_TDM0_TXQ        MPP(33, 0x6, 0, 1, 1)
++#define MPP33_UA3_RDX        MPP(33, 0x4, 0, 0, 1)
++#define MPP33_TDM0_TXQ        MPP(33, 0x6, 0, 0, 1)
+ #define MPP33_UNUSED        MPP(33, 0x3, 0, 0, 1)
+ 
+ 
+ 
+ #define MPP34_GPIO        MPP(34, 0x1, 1, 1, 1)
+-#define MPP34_UA2_TDX        MPP(34, 0x4, 0, 1, 1)
+-#define MPP34_TDM1_RXQ        MPP(34, 0x6, 0, 1, 1)
++#define MPP34_UA2_TDX        MPP(34, 0x4, 0, 0, 1)
++#define MPP34_TDM1_RXQ        MPP(34, 0x6, 0, 0, 1)
+ #define MPP34_UNUSED        MPP(34, 0x3, 0, 0, 1)
+ 
+ 
+ 
+ #define MPP35_GPIO        MPP(35, 0x1, 1, 1, 1)
+-#define MPP35_UA2_RDX        MPP(35, 0x4, 1, 0, 1)
+-#define MPP35_TDM1_TXQ        MPP(35, 0x6, 0, 1, 1)
++#define MPP35_UA2_RDX        MPP(35, 0x4, 0, 0, 1)
++#define MPP35_TDM1_TXQ        MPP(35, 0x6, 0, 0, 1)
+ #define MPP35_UNUSED        MPP(35, 0x3, 0, 0, 1)
+ 
+ #define MPP36_GPIO        MPP(36, 0x1, 1, 1, 1)
+-#define MPP36_UA0_CTSn        MPP(36, 0x2, 1, 0, 1)
+-#define MPP36_UA2_TDX        MPP(36, 0x4, 0, 1, 1)
+-#define MPP36_TDM0_SCSn        MPP(36, 0x6, 0, 1, 1)
++#define MPP36_UA0_CTSn        MPP(36, 0x2, 0, 0, 1)
++#define MPP36_UA2_TDX        MPP(36, 0x4, 0, 0, 1)
++#define MPP36_TDM0_SCSn        MPP(36, 0x6, 0, 0, 1)
+ #define MPP36_UNUSED        MPP(36, 0x3, 0, 0, 1)
+ 
+ 
+ #define MPP37_GPIO        MPP(37, 0x1, 1, 1, 1)
+-#define MPP37_UA0_RTSn        MPP(37, 0x2, 0, 1, 1)
+-#define MPP37_UA2_RXD        MPP(37, 0x4, 1, 0, 1)
+-#define MPP37_SYSRST_OUTn    MPP(37, 0x5, 0, 1, 1)
+-#define MPP37_TDM_SCLK        MPP(37, 0x6, 0, 1, 1)
++#define MPP37_UA0_RTSn        MPP(37, 0x2, 0, 0, 1)
++#define MPP37_UA2_RXD        MPP(37, 0x4, 0, 0, 1)
++#define MPP37_SYSRST_OUTn    MPP(37, 0x5, 0, 0, 1)
++#define MPP37_TDM_SCLK        MPP(37, 0x6, 0, 0, 1)
+ #define MPP37_UNUSED        MPP(37, 0x3, 0, 0, 1)
+ 
+ 
+ 
+ 
+ #define MPP38_GPIO        MPP(38, 0x1, 1, 1, 1)
+-#define MPP38_UA1_CTSn        MPP(38, 0x2, 1, 0, 1)
+-#define MPP38_UA3_TXD        MPP(38, 0x4, 0, 1, 1)
+-#define MPP38_SYSRST_OUTn    MPP(38, 0x5, 0, 1, 1)
+-#define MPP38_TDM_SMOSI        MPP(38, 0x6, 0, 1, 1)
++#define MPP38_UA1_CTSn        MPP(38, 0x2, 0, 0, 1)
++#define MPP38_UA3_TXD        MPP(38, 0x4, 0, 0, 1)
++#define MPP38_SYSRST_OUTn    MPP(38, 0x5, 0, 0, 1)
++#define MPP38_TDM_SMOSI        MPP(38, 0x6, 0, 0, 1)
+ #define MPP38_UNUSED        MPP(38, 0x3, 0, 0, 1)
+ 
+ 
+ 
+ 
+ #define MPP39_GPIO        MPP(39, 0x1, 1, 1, 1)
+-#define MPP39_UA1_RTSn        MPP(39, 0x2, 0, 1, 1)
+-#define MPP39_UA3_RXD        MPP(39, 0x4, 1, 0, 1)
+-#define MPP39_SYSRST_OUTn    MPP(39, 0x5, 0, 1, 1)
+-#define MPP39_TDM_SMISO        MPP(39, 0x6, 1, 0, 1)
++#define MPP39_UA1_RTSn        MPP(39, 0x2, 0, 0, 1)
++#define MPP39_UA3_RXD        MPP(39, 0x4, 0, 0, 1)
++#define MPP39_SYSRST_OUTn    MPP(39, 0x5, 0, 0, 1)
++#define MPP39_TDM_SMISO        MPP(39, 0x6, 0, 0, 1)
+ #define MPP39_UNUSED        MPP(39, 0x3, 0, 0, 1)
+ 
+ 
+ 
+ #define MPP40_GPIO        MPP(40, 0x1, 1, 1, 1)
+-#define MPP40_TDM_INTn        MPP(40, 0x6, 1, 0, 1)
++#define MPP40_TDM_INTn        MPP(40, 0x6, 0, 0, 1)
+ #define MPP40_UNUSED        MPP(40, 0x0, 0, 0, 1)
+ 
+ 
+ 
+ #define MPP41_GPIO        MPP(41, 0x1, 1, 1, 1)
+-#define MPP41_TDM_RSTn        MPP(41, 0x6, 0, 1, 1)
++#define MPP41_TDM_RSTn        MPP(41, 0x6, 0, 0, 1)
+ #define MPP41_UNUSED        MPP(41, 0x0, 0, 0, 1)
+ 
+ 
+ 
+ #define MPP42_GPIO        MPP(42, 0x1, 1, 1, 1)
+-#define MPP42_TDM_PCLK        MPP(42, 0x6, 1, 1, 1)
++#define MPP42_TDM_PCLK        MPP(42, 0x6, 0, 0, 1)
+ #define MPP42_UNUSED        MPP(42, 0x0, 0, 0, 1)
+ 
+ 
+ 
+ #define MPP43_GPIO        MPP(43, 0x1, 1, 1, 1)
+-#define MPP43_TDM_FSYNC        MPP(43, 0x6, 1, 1, 1)
++#define MPP43_TDM_FSYNC        MPP(43, 0x6, 0, 0, 1)
+ #define MPP43_UNUSED        MPP(43, 0x0, 0, 0, 1)
+ 
+ 
+ 
+ #define MPP44_GPIO        MPP(44, 0x1, 1, 1, 1)
+-#define MPP44_TDM_DRX        MPP(44, 0x6, 1, 0, 1)
++#define MPP44_TDM_DRX        MPP(44, 0x6, 0, 0, 1)
+ #define MPP44_UNUSED        MPP(44, 0x0, 0, 0, 1)
+ 
+ 
+ 
+ #define MPP45_GPIO        MPP(45, 0x1, 1, 1, 1)
+-#define MPP45_SATA0_ACTn    MPP(45, 0x3, 0, 1, 1)
+-#define MPP45_TDM_DRX        MPP(45, 0x6, 0, 1, 1)
++#define MPP45_SATA0_ACTn    MPP(45, 0x3, 0, 0, 1)
++#define MPP45_TDM_DRX        MPP(45, 0x6, 0, 0, 1)
+ #define MPP45_UNUSED        MPP(45, 0x0, 0, 0, 1)
+ 
+ 
+ #define MPP46_GPIO        MPP(46, 0x1, 1, 1, 1)
+-#define MPP46_TDM_SCSn        MPP(46, 0x6, 0, 1, 1)
++#define MPP46_TDM_SCSn        MPP(46, 0x6, 0, 0, 1)
+ #define MPP46_UNUSED        MPP(46, 0x0, 0, 0, 1)
+ 
+ 
+@@ -323,14 +323,14 @@
+ 
+ 
+ #define MPP48_GPIO        MPP(48, 0x1, 1, 1, 1)
+-#define MPP48_SATA1_ACTn    MPP(48, 0x3, 0, 1, 1)
++#define MPP48_SATA1_ACTn    MPP(48, 0x3, 0, 0, 1)
+ #define MPP48_UNUSED        MPP(48, 0x2, 0, 0, 1)
+ 
+ 
+ 
+ #define MPP49_GPIO        MPP(49, 0x1, 1, 1, 1)
+-#define MPP49_SATA0_ACTn    MPP(49, 0x3, 0, 1, 1)
+-#define MPP49_M_BB        MPP(49, 0x4, 1, 0, 1)
++#define MPP49_SATA0_ACTn    MPP(49, 0x3, 0, 0, 1)
++#define MPP49_M_BB        MPP(49, 0x4, 0, 0, 1)
+ #define MPP49_UNUSED        MPP(49, 0x2, 0, 0, 1)
+ 
+ 
+--- a/arch/arm/plat-orion/mpp.c
++++ b/arch/arm/plat-orion/mpp.c
+@@ -64,8 +64,7 @@ void __init orion_mpp_conf(unsigned int
+                       gpio_mode |= GPIO_INPUT_OK;
+               if (*mpp_list & MPP_OUTPUT_MASK)
+                       gpio_mode |= GPIO_OUTPUT_OK;
+-              if (sel != 0)
+-                      gpio_mode = 0;
++
+               orion_gpio_set_valid(num, gpio_mode);
+       }
+ 

diff --git a/queue-3.0/arm-orion-fix-usb-phy-for-orion5x.patch b/queue-3.0/arm-orion-fix-usb-phy-for-orion5x.patch
new file mode 100644 (file)
index 0000000..746dca0
--- /dev/null
+++ b/queue-3.0/arm-orion-fix-usb-phy-for-orion5x.patch
@@ -0,0 +1,153 @@
+From 72053353583230952c4b187e110e9da00dfc3afb Mon Sep 17 00:00:00 2001
+From: Andrew Lunn <andrew@lunn.ch>
+Date: Wed, 8 Feb 2012 15:52:47 +0100
+Subject: ARM: orion: Fix USB phy for orion5x.
+
+From: Andrew Lunn <andrew@lunn.ch>
+
+commit 72053353583230952c4b187e110e9da00dfc3afb upstream.
+
+The patch "ARM: orion: Consolidate USB platform setup code.", commit
+4fcd3f374a928081d391cd9a570afe3b2c692fdc broke USB on TS-7800 and
+other orion5x boards, because the wrong type of PHY was being passed
+to the EHCI driver in the platform data. Orion5x needs EHCI_PHY_ORION
+and all the others want EHCI_PHY_NA.
+
+Allow the mach- code to tell the generic plat-orion code which USB PHY
+enum to place into the platform data.
+
+Version 2: Rebase to v3.3-rc2.
+
+Reported-by: Ambroz Bizjak <ambrop7@gmail.com>
+Signed-off-by: Andrew Lunn <andrew@lunn.ch>
+Tested-by: Ambroz Bizjak <ambrop7@gmail.com>
+Acked-by: Nicolas Pitre <nico@linaro.org>
+Signed-off-by: Olof Johansson <olof@lixom.net>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+
+---
+ arch/arm/mach-dove/common.c               |    3 ++-
+ arch/arm/mach-kirkwood/common.c           |    3 ++-
+ arch/arm/mach-mv78xx0/common.c            |    3 ++-
+ arch/arm/mach-orion5x/common.c            |    4 +++-
+ arch/arm/plat-orion/common.c              |    9 ++++-----
+ arch/arm/plat-orion/include/plat/common.h |    3 ++-
+ 6 files changed, 15 insertions(+), 10 deletions(-)
+
+--- a/arch/arm/mach-dove/common.c
++++ b/arch/arm/mach-dove/common.c
+@@ -31,6 +31,7 @@
+ #include <asm/mach/arch.h>
+ #include <linux/irq.h>
+ #include <plat/time.h>
++#include <plat/ehci-orion.h>
+ #include <plat/common.h>
+ #include "common.h"
+ 
+@@ -74,7 +75,7 @@ void __init dove_map_io(void)
+ void __init dove_ehci0_init(void)
+ {
+       orion_ehci_init(&dove_mbus_dram_info,
+-                      DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0);
++                      DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0, EHCI_PHY_NA);
+ }
+ 
+ /*****************************************************************************
+--- a/arch/arm/mach-kirkwood/common.c
++++ b/arch/arm/mach-kirkwood/common.c
+@@ -28,6 +28,7 @@
+ #include <plat/cache-feroceon-l2.h>
+ #include <plat/mvsdio.h>
+ #include <plat/orion_nand.h>
++#include <plat/ehci-orion.h>
+ #include <plat/common.h>
+ #include <plat/time.h>
+ #include "common.h"
+@@ -74,7 +75,7 @@ void __init kirkwood_ehci_init(void)
+ {
+       kirkwood_clk_ctrl |= CGC_USB0;
+       orion_ehci_init(&kirkwood_mbus_dram_info,
+-                      USB_PHYS_BASE, IRQ_KIRKWOOD_USB);
++                      USB_PHYS_BASE, IRQ_KIRKWOOD_USB, EHCI_PHY_NA);
+ }
+ 
+ 
+--- a/arch/arm/mach-mv78xx0/common.c
++++ b/arch/arm/mach-mv78xx0/common.c
+@@ -20,6 +20,7 @@
+ #include <mach/mv78xx0.h>
+ #include <mach/bridge-regs.h>
+ #include <plat/cache-feroceon-l2.h>
++#include <plat/ehci-orion.h>
+ #include <plat/orion_nand.h>
+ #include <plat/time.h>
+ #include <plat/common.h>
+@@ -170,7 +171,7 @@ void __init mv78xx0_map_io(void)
+ void __init mv78xx0_ehci0_init(void)
+ {
+       orion_ehci_init(&mv78xx0_mbus_dram_info,
+-                      USB0_PHYS_BASE, IRQ_MV78XX0_USB_0);
++                      USB0_PHYS_BASE, IRQ_MV78XX0_USB_0, EHCI_PHY_NA);
+ }
+ 
+ 
+--- a/arch/arm/mach-orion5x/common.c
++++ b/arch/arm/mach-orion5x/common.c
+@@ -29,6 +29,7 @@
+ #include <mach/hardware.h>
+ #include <mach/orion5x.h>
+ #include <plat/orion_nand.h>
++#include <plat/ehci-orion.h>
+ #include <plat/time.h>
+ #include <plat/common.h>
+ #include "common.h"
+@@ -72,7 +73,8 @@ void __init orion5x_map_io(void)
+ void __init orion5x_ehci0_init(void)
+ {
+       orion_ehci_init(&orion5x_mbus_dram_info,
+-                      ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL);
++                      ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL,
++                      EHCI_PHY_ORION);
+ }
+ 
+ 
+--- a/arch/arm/plat-orion/common.c
++++ b/arch/arm/plat-orion/common.c
+@@ -806,10 +806,7 @@ void __init orion_xor1_init(unsigned lon
+ /*****************************************************************************
+  * EHCI
+  ****************************************************************************/
+-static struct orion_ehci_data orion_ehci_data = {
+-      .phy_version    = EHCI_PHY_NA,
+-};
+-
++static struct orion_ehci_data orion_ehci_data;
+ static u64 ehci_dmamask = DMA_BIT_MASK(32);
+ 
+ 
+@@ -830,9 +827,11 @@ static struct platform_device orion_ehci
+ 
+ void __init orion_ehci_init(struct mbus_dram_target_info *mbus_dram_info,
+                           unsigned long mapbase,
+-                          unsigned long irq)
++                          unsigned long irq,
++                          enum orion_ehci_phy_ver phy_version)
+ {
+       orion_ehci_data.dram = mbus_dram_info;
++      orion_ehci_data.phy_version = phy_version;
+       fill_resources(&orion_ehci, orion_ehci_resources, mapbase, SZ_4K - 1,
+                      irq);
+ 
+--- a/arch/arm/plat-orion/include/plat/common.h
++++ b/arch/arm/plat-orion/include/plat/common.h
+@@ -95,7 +95,8 @@ void __init orion_xor1_init(unsigned lon
+ 
+ void __init orion_ehci_init(struct mbus_dram_target_info *mbus_dram_info,
+                           unsigned long mapbase,
+-                          unsigned long irq);
++                          unsigned long irq,
++                          enum orion_ehci_phy_ver phy_version);
+ 
+ void __init orion_ehci_1_init(struct mbus_dram_target_info *mbus_dram_info,
+                             unsigned long mapbase,

diff --git a/queue-3.0/omap-4430sdp-panda-use-gpio_free_array-to-free-hdmi-gpios.patch b/queue-3.0/omap-4430sdp-panda-use-gpio_free_array-to-free-hdmi-gpios.patch
new file mode 100644 (file)
index 0000000..b2a47c8
--- /dev/null
+++ b/queue-3.0/omap-4430sdp-panda-use-gpio_free_array-to-free-hdmi-gpios.patch
@@ -0,0 +1,44 @@
+From 575753e3bea3b67eef8e454fb87f719e3f7da599 Mon Sep 17 00:00:00 2001
+From: Tomi Valkeinen <tomi.valkeinen@ti.com>
+Date: Tue, 17 Jan 2012 11:04:53 +0200
+Subject: OMAP: 4430SDP/Panda: use gpio_free_array to free HDMI gpios
+
+From: Tomi Valkeinen <tomi.valkeinen@ti.com>
+
+commit 575753e3bea3b67eef8e454fb87f719e3f7da599 upstream.
+
+Instead of freeing the GPIOs individually, use gpio_free_array().
+
+Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
+Acked-by: Tony Lindgren <tony@atomide.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm/mach-omap2/board-4430sdp.c    |    3 +--
+ arch/arm/mach-omap2/board-omap4panda.c |    3 +--
+ 2 files changed, 2 insertions(+), 4 deletions(-)
+
+--- a/arch/arm/mach-omap2/board-4430sdp.c
++++ b/arch/arm/mach-omap2/board-4430sdp.c
+@@ -609,8 +609,7 @@ static int sdp4430_panel_enable_hdmi(str
+ 
+ static void sdp4430_panel_disable_hdmi(struct omap_dss_device *dssdev)
+ {
+-      gpio_free(HDMI_GPIO_LS_OE);
+-      gpio_free(HDMI_GPIO_HPD);
++      gpio_free_array(sdp4430_hdmi_gpios, ARRAY_SIZE(sdp4430_hdmi_gpios));
+ }
+ 
+ static struct omap_dss_device sdp4430_hdmi_device = {
+--- a/arch/arm/mach-omap2/board-omap4panda.c
++++ b/arch/arm/mach-omap2/board-omap4panda.c
+@@ -645,8 +645,7 @@ static int omap4_panda_panel_enable_hdmi
+ 
+ static void omap4_panda_panel_disable_hdmi(struct omap_dss_device *dssdev)
+ {
+-      gpio_free(HDMI_GPIO_LS_OE);
+-      gpio_free(HDMI_GPIO_HPD);
++      gpio_free_array(panda_hdmi_gpios, ARRAY_SIZE(panda_hdmi_gpios));
+ }
+ 
+ static struct omap_dss_device  omap4_panda_hdmi_device = {

diff --git a/queue-3.0/series b/queue-3.0/series
index fafc7bef23c7fa64fcbf344fd25cf495825f7e51..700d96a512255776d4bf740c52fb808089d183f5 100644 (file)
--- a/queue-3.0/series
+++ b/queue-3.0/series
@@ -41,3 +41,6 @@ drm-i915-gen7-implement-rczunit-workaround.patch
 drm-i915-gen7-implement-an-l3-caching-workaround.patch
 drm-i915-gen7-work-around-a-system-hang-on-ivb.patch
 drm-i915-gen7-disable-the-rhwo-optimization-as-it-can-cause-gpu-hangs.patch
+arm-orion-fix-usb-phy-for-orion5x.patch
+arm-orion-fix-orion5x-gpio-regression-from-mpp-cleanup.patch
+omap-4430sdp-panda-use-gpio_free_array-to-free-hdmi-gpios.patch