drm/i915/dp: Enable 3 DSC engines for 12 slices

Certain resolutions require 12 DSC slices support along with ultrajoiner.
For such cases, the third DSC Engine per Pipe is enabled. Each DSC
Engine processes 1 Slice, resulting in a total of 12 VDSC slices
(4 Pipes * 3 DSC Instances per Pipe).
Add support for 12 DSC slices and 3 DSC engines for such modes.

v2: Add missing check for 3 slices support only with 4 joined pipes.
(Suraj)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241030041036.1238006-8-ankit.k.nautiyal@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 303852d469e8f82c93c501c6efe702f7df106d7d..5b918363df16ee99244eee632deaaddd004b2392 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -116,9 +116,12 @@ static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
  * For now consider a max of 2 slices per line, which works for all platforms.
  * With this we can have max of 4 DSC Slices per pipe.
  *
+ * For higher resolutions where 12 slice support is required with
+ * ultrajoiner, only then each pipe can support 3 slices.
+ *
  * #TODO Split this better to use 4 slices/dsc engine where supported.
  */
-static const u8 valid_dsc_slicecount[] = {1, 2, 4};
+static const u8 valid_dsc_slicecount[] = {1, 2, 3, 4};
 
 /**
  * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
@@ -1026,6 +1029,13 @@ u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector,
        for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
                u8 test_slice_count = valid_dsc_slicecount[i] * num_joined_pipes;
 
+               /*
+                * 3 DSC Slices per pipe need 3 DSC engines,
+                * which is supported only with Ultrajoiner.
+                */
+               if (valid_dsc_slicecount[i] == 3 && num_joined_pipes != 4)
+                       continue;
+
                if (test_slice_count >
                    drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd, false))
                        break;
@@ -2414,8 +2424,13 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
         * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
         * is greater than the maximum Cdclock and if slice count is even
         * then we need to use 2 VDSC instances.
+        * In case of Ultrajoiner along with 12 slices we need to use 3
+        * VDSC instances.
         */
-       if (pipe_config->joiner_pipes || pipe_config->dsc.slice_count > 1)
+       if (pipe_config->joiner_pipes && num_joined_pipes == 4 &&
+           pipe_config->dsc.slice_count == 12)
+               pipe_config->dsc.num_streams = 3;
+       else if (pipe_config->joiner_pipes || pipe_config->dsc.slice_count > 1)
                pipe_config->dsc.num_streams = 2;
        else
                pipe_config->dsc.num_streams = 1;