clk: qcom: ipq5332: remove q6 bring up clocks

Q6 firmware takes care of bringup clocks, so remove them from gcc driver.

Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>
Link: https://lore.kernel.org/r/20240820055618.267554-2-quic_gokulsri@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/drivers/clk/qcom/gcc-ipq5332.c b/drivers/clk/qcom/gcc-ipq5332.c
index 00c48478c8876bd4cd416d9b6a05f679c0c8c747..9246e97d785a1f56b2fa4464011af5f3d8409e19 100644 (file)
--- a/drivers/clk/qcom/gcc-ipq5332.c
+++ b/drivers/clk/qcom/gcc-ipq5332.c
@@ -2185,150 +2185,6 @@ static struct clk_branch gcc_prng_ahb_clk = {
        },
 };
 
-static struct clk_branch gcc_q6_ahb_clk = {
-       .halt_reg = 0x25014,
-       .halt_check = BRANCH_HALT_VOTED,
-       .clkr = {
-               .enable_reg = 0x25014,
-               .enable_mask = BIT(0),
-               .hw.init = &(const struct clk_init_data) {
-                       .name = "gcc_q6_ahb_clk",
-                       .parent_hws = (const struct clk_hw*[]) {
-                               &gcc_wcss_ahb_clk_src.clkr.hw,
-                       },
-                       .num_parents = 1,
-                       .flags = CLK_SET_RATE_PARENT,
-                       .ops = &clk_branch2_ops,
-               },
-       },
-};
-
-static struct clk_branch gcc_q6_ahb_s_clk = {
-       .halt_reg = 0x25018,
-       .halt_check = BRANCH_HALT_VOTED,
-       .clkr = {
-               .enable_reg = 0x25018,
-               .enable_mask = BIT(0),
-               .hw.init = &(const struct clk_init_data) {
-                       .name = "gcc_q6_ahb_s_clk",
-                       .parent_hws = (const struct clk_hw*[]) {
-                               &gcc_wcss_ahb_clk_src.clkr.hw,
-                       },
-                       .num_parents = 1,
-                       .flags = CLK_SET_RATE_PARENT,
-                       .ops = &clk_branch2_ops,
-               },
-       },
-};
-
-static struct clk_branch gcc_q6_axim_clk = {
-       .halt_reg = 0x2500c,
-       .halt_check = BRANCH_HALT_VOTED,
-       .clkr = {
-               .enable_reg = 0x2500c,
-               .enable_mask = BIT(0),
-               .hw.init = &(const struct clk_init_data) {
-                       .name = "gcc_q6_axim_clk",
-                       .parent_hws = (const struct clk_hw*[]) {
-                               &gcc_q6_axim_clk_src.clkr.hw,
-                       },
-                       .num_parents = 1,
-                       .flags = CLK_SET_RATE_PARENT,
-                       .ops = &clk_branch2_ops,
-               },
-       },
-};
-
-static struct clk_branch gcc_q6_axis_clk = {
-       .halt_reg = 0x25010,
-       .halt_check = BRANCH_HALT_VOTED,
-       .clkr = {
-               .enable_reg = 0x25010,
-               .enable_mask = BIT(0),
-               .hw.init = &(const struct clk_init_data) {
-                       .name = "gcc_q6_axis_clk",
-                       .parent_hws = (const struct clk_hw*[]) {
-                               &gcc_system_noc_bfdcd_clk_src.clkr.hw,
-                       },
-                       .num_parents = 1,
-                       .flags = CLK_SET_RATE_PARENT,
-                       .ops = &clk_branch2_ops,
-               },
-       },
-};
-
-static struct clk_branch gcc_q6_tsctr_1to2_clk = {
-       .halt_reg = 0x25020,
-       .halt_check = BRANCH_HALT_VOTED,
-       .clkr = {
-               .enable_reg = 0x25020,
-               .enable_mask = BIT(0),
-               .hw.init = &(const struct clk_init_data) {
-                       .name = "gcc_q6_tsctr_1to2_clk",
-                       .parent_hws = (const struct clk_hw*[]) {
-                               &gcc_qdss_tsctr_div2_clk_src.hw,
-                       },
-                       .num_parents = 1,
-                       .flags = CLK_SET_RATE_PARENT,
-                       .ops = &clk_branch2_ops,
-               },
-       },
-};
-
-static struct clk_branch gcc_q6ss_atbm_clk = {
-       .halt_reg = 0x2501c,
-       .halt_check = BRANCH_HALT_VOTED,
-       .clkr = {
-               .enable_reg = 0x2501c,
-               .enable_mask = BIT(0),
-               .hw.init = &(const struct clk_init_data) {
-                       .name = "gcc_q6ss_atbm_clk",
-                       .parent_hws = (const struct clk_hw*[]) {
-                               &gcc_qdss_at_clk_src.clkr.hw,
-                       },
-                       .num_parents = 1,
-                       .flags = CLK_SET_RATE_PARENT,
-                       .ops = &clk_branch2_ops,
-               },
-       },
-};
-
-static struct clk_branch gcc_q6ss_pclkdbg_clk = {
-       .halt_reg = 0x25024,
-       .halt_check = BRANCH_HALT_VOTED,
-       .clkr = {
-               .enable_reg = 0x25024,
-               .enable_mask = BIT(0),
-               .hw.init = &(const struct clk_init_data) {
-                       .name = "gcc_q6ss_pclkdbg_clk",
-                       .parent_hws = (const struct clk_hw*[]) {
-                               &gcc_qdss_dap_div_clk_src.clkr.hw,
-                       },
-                       .num_parents = 1,
-                       .flags = CLK_SET_RATE_PARENT,
-                       .ops = &clk_branch2_ops,
-               },
-       },
-};
-
-static struct clk_branch gcc_q6ss_trig_clk = {
-       .halt_reg = 0x250a0,
-       .halt_check = BRANCH_HALT_VOTED,
-       .clkr = {
-               .enable_reg = 0x250a0,
-               .enable_mask = BIT(0),
-               .hw.init = &(const struct clk_init_data) {
-                       .name = "gcc_q6ss_trig_clk",
-                       .parent_hws = (const struct clk_hw*[]) {
-                               &gcc_qdss_dap_div_clk_src.clkr.hw,
-                       },
-                       .num_parents = 1,
-                       .flags = CLK_SET_RATE_PARENT,
-                       .ops = &clk_branch2_ops,
-               },
-       },
-};
-
 static struct clk_branch gcc_qdss_at_clk = {
        .halt_reg = 0x2d038,
        .halt_check = BRANCH_HALT_VOTED,
@@ -2756,24 +2612,6 @@ static struct clk_branch gcc_sys_noc_at_clk = {
        },
 };
 
-static struct clk_branch gcc_sys_noc_wcss_ahb_clk = {
-       .halt_reg = 0x2e030,
-       .halt_check = BRANCH_HALT,
-       .clkr = {
-               .enable_reg = 0x2e030,
-               .enable_mask = BIT(0),
-               .hw.init = &(const struct clk_init_data) {
-                       .name = "gcc_sys_noc_wcss_ahb_clk",
-                       .parent_hws = (const struct clk_hw*[]) {
-                               &gcc_wcss_ahb_clk_src.clkr.hw,
-                       },
-                       .num_parents = 1,
-                       .flags = CLK_SET_RATE_PARENT,
-                       .ops = &clk_branch2_ops,
-               },
-       },
-};
-
 static struct clk_branch gcc_uniphy0_ahb_clk = {
        .halt_reg = 0x16010,
        .halt_check = BRANCH_HALT,
@@ -2989,204 +2827,6 @@ static struct clk_branch gcc_usb0_sleep_clk = {
        },
 };
 
-static struct clk_branch gcc_wcss_axim_clk = {
-       .halt_reg = 0x2505c,
-       .halt_check = BRANCH_HALT,
-       .clkr = {
-               .enable_reg = 0x2505c,
-               .enable_mask = BIT(0),
-               .hw.init = &(const struct clk_init_data) {
-                       .name = "gcc_wcss_axim_clk",
-                       .parent_hws = (const struct clk_hw*[]) {
-                               &gcc_system_noc_bfdcd_clk_src.clkr.hw,
-                       },
-                       .num_parents = 1,
-                       .flags = CLK_SET_RATE_PARENT,
-                       .ops = &clk_branch2_ops,
-               },
-       },
-};
-
-static struct clk_branch gcc_wcss_axis_clk = {
-       .halt_reg = 0x25060,
-       .halt_check = BRANCH_HALT,
-       .clkr = {
-               .enable_reg = 0x25060,
-               .enable_mask = BIT(0),
-               .hw.init = &(const struct clk_init_data) {
-                       .name = "gcc_wcss_axis_clk",
-                       .parent_hws = (const struct clk_hw*[]) {
-                               &gcc_system_noc_bfdcd_clk_src.clkr.hw,
-                       },
-                       .num_parents = 1,
-                       .flags = CLK_SET_RATE_PARENT,
-                       .ops = &clk_branch2_ops,
-               },
-       },
-};
-
-static struct clk_branch gcc_wcss_dbg_ifc_apb_bdg_clk = {
-       .halt_reg = 0x25048,
-       .halt_check = BRANCH_HALT,
-       .clkr = {
-               .enable_reg = 0x25048,
-               .enable_mask = BIT(0),
-               .hw.init = &(const struct clk_init_data) {
-                       .name = "gcc_wcss_dbg_ifc_apb_bdg_clk",
-                       .parent_hws = (const struct clk_hw*[]) {
-                               &gcc_qdss_dap_div_clk_src.clkr.hw,
-                       },
-                       .num_parents = 1,
-                       .flags = CLK_SET_RATE_PARENT,
-                       .ops = &clk_branch2_ops,
-               },
-       },
-};
-
-static struct clk_branch gcc_wcss_dbg_ifc_apb_clk = {
-       .halt_reg = 0x25038,
-       .halt_check = BRANCH_HALT,
-       .clkr = {
-               .enable_reg = 0x25038,
-               .enable_mask = BIT(0),
-               .hw.init = &(const struct clk_init_data) {
-                       .name = "gcc_wcss_dbg_ifc_apb_clk",
-                       .parent_hws = (const struct clk_hw*[]) {
-                               &gcc_qdss_dap_div_clk_src.clkr.hw,
-                       },
-                       .num_parents = 1,
-                       .flags = CLK_SET_RATE_PARENT,
-                       .ops = &clk_branch2_ops,
-               },
-       },
-};
-
-static struct clk_branch gcc_wcss_dbg_ifc_atb_bdg_clk = {
-       .halt_reg = 0x2504c,
-       .halt_check = BRANCH_HALT,
-       .clkr = {
-               .enable_reg = 0x2504c,
-               .enable_mask = BIT(0),
-               .hw.init = &(const struct clk_init_data) {
-                       .name = "gcc_wcss_dbg_ifc_atb_bdg_clk",
-                       .parent_hws = (const struct clk_hw*[]) {
-                               &gcc_qdss_at_clk_src.clkr.hw,
-                       },
-                       .num_parents = 1,
-                       .flags = CLK_SET_RATE_PARENT,
-                       .ops = &clk_branch2_ops,
-               },
-       },
-};
-
-static struct clk_branch gcc_wcss_dbg_ifc_atb_clk = {
-       .halt_reg = 0x2503c,
-       .halt_check = BRANCH_HALT,
-       .clkr = {
-               .enable_reg = 0x2503c,
-               .enable_mask = BIT(0),
-               .hw.init = &(const struct clk_init_data) {
-                       .name = "gcc_wcss_dbg_ifc_atb_clk",
-                       .parent_hws = (const struct clk_hw*[]) {
-                               &gcc_qdss_at_clk_src.clkr.hw,
-                       },
-                       .num_parents = 1,
-                       .flags = CLK_SET_RATE_PARENT,
-                       .ops = &clk_branch2_ops,
-               },
-       },
-};
-
-static struct clk_branch gcc_wcss_dbg_ifc_nts_bdg_clk = {
-       .halt_reg = 0x25050,
-       .halt_check = BRANCH_HALT,
-       .clkr = {
-               .enable_reg = 0x25050,
-               .enable_mask = BIT(0),
-               .hw.init = &(const struct clk_init_data) {
-                       .name = "gcc_wcss_dbg_ifc_nts_bdg_clk",
-                       .parent_hws = (const struct clk_hw*[]) {
-                               &gcc_qdss_tsctr_div2_clk_src.hw,
-                       },
-                       .num_parents = 1,
-                       .flags = CLK_SET_RATE_PARENT,
-                       .ops = &clk_branch2_ops,
-               },
-       },
-};
-
-static struct clk_branch gcc_wcss_dbg_ifc_nts_clk = {
-       .halt_reg = 0x25040,
-       .halt_check = BRANCH_HALT,
-       .clkr = {
-               .enable_reg = 0x25040,
-               .enable_mask = BIT(0),
-               .hw.init = &(const struct clk_init_data) {
-                       .name = "gcc_wcss_dbg_ifc_nts_clk",
-                       .parent_hws = (const struct clk_hw*[]) {
-                               &gcc_qdss_tsctr_div2_clk_src.hw,
-                       },
-                       .num_parents = 1,
-                       .flags = CLK_SET_RATE_PARENT,
-                       .ops = &clk_branch2_ops,
-               },
-       },
-};
-
-static struct clk_branch gcc_wcss_ecahb_clk = {
-       .halt_reg = 0x25058,
-       .halt_check = BRANCH_HALT,
-       .clkr = {
-               .enable_reg = 0x25058,
-               .enable_mask = BIT(0),
-               .hw.init = &(const struct clk_init_data) {
-                       .name = "gcc_wcss_ecahb_clk",
-                       .parent_hws = (const struct clk_hw*[]) {
-                               &gcc_wcss_ahb_clk_src.clkr.hw,
-                       },
-                       .num_parents = 1,
-                       .flags = CLK_SET_RATE_PARENT,
-                       .ops = &clk_branch2_ops,
-               },
-       },
-};
-
-static struct clk_branch gcc_wcss_mst_async_bdg_clk = {
-       .halt_reg = 0x2e0b0,
-       .halt_check = BRANCH_HALT,
-       .clkr = {
-               .enable_reg = 0x2e0b0,
-               .enable_mask = BIT(0),
-               .hw.init = &(const struct clk_init_data) {
-                       .name = "gcc_wcss_mst_async_bdg_clk",
-                       .parent_hws = (const struct clk_hw*[]) {
-                               &gcc_system_noc_bfdcd_clk_src.clkr.hw,
-                       },
-                       .num_parents = 1,
-                       .flags = CLK_SET_RATE_PARENT,
-                       .ops = &clk_branch2_ops,
-               },
-       },
-};
-
-static struct clk_branch gcc_wcss_slv_async_bdg_clk = {
-       .halt_reg = 0x2e0b4,
-       .halt_check = BRANCH_HALT,
-       .clkr = {
-               .enable_reg = 0x2e0b4,
-               .enable_mask = BIT(0),
-               .hw.init = &(const struct clk_init_data) {
-                       .name = "gcc_wcss_slv_async_bdg_clk",
-                       .parent_hws = (const struct clk_hw*[]) {
-                               &gcc_system_noc_bfdcd_clk_src.clkr.hw,
-                       },
-                       .num_parents = 1,
-                       .flags = CLK_SET_RATE_PARENT,
-                       .ops = &clk_branch2_ops,
-               },
-       },
-};
-
 static struct clk_branch gcc_xo_clk = {
        .halt_reg = 0x34018,
        .halt_check = BRANCH_HALT,
@@ -3362,15 +3002,7 @@ static struct clk_regmap *gcc_ipq5332_clocks[] = {
        [GCC_PCNOC_BFDCD_CLK_SRC] = &gcc_pcnoc_bfdcd_clk_src.clkr,
        [GCC_PCNOC_LPASS_CLK] = &gcc_pcnoc_lpass_clk.clkr,
        [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
-       [GCC_Q6_AHB_CLK] = &gcc_q6_ahb_clk.clkr,
-       [GCC_Q6_AHB_S_CLK] = &gcc_q6_ahb_s_clk.clkr,
-       [GCC_Q6_AXIM_CLK] = &gcc_q6_axim_clk.clkr,
        [GCC_Q6_AXIM_CLK_SRC] = &gcc_q6_axim_clk_src.clkr,
-       [GCC_Q6_AXIS_CLK] = &gcc_q6_axis_clk.clkr,
-       [GCC_Q6_TSCTR_1TO2_CLK] = &gcc_q6_tsctr_1to2_clk.clkr,
-       [GCC_Q6SS_ATBM_CLK] = &gcc_q6ss_atbm_clk.clkr,
-       [GCC_Q6SS_PCLKDBG_CLK] = &gcc_q6ss_pclkdbg_clk.clkr,
-       [GCC_Q6SS_TRIG_CLK] = &gcc_q6ss_trig_clk.clkr,
        [GCC_QDSS_AT_CLK] = &gcc_qdss_at_clk.clkr,
        [GCC_QDSS_AT_CLK_SRC] = &gcc_qdss_at_clk_src.clkr,
        [GCC_QDSS_CFG_AHB_CLK] = &gcc_qdss_cfg_ahb_clk.clkr,
@@ -3400,7 +3032,6 @@ static struct clk_regmap *gcc_ipq5332_clocks[] = {
        [GCC_SNOC_PCIE3_2LANE_S_CLK] = &gcc_snoc_pcie3_2lane_s_clk.clkr,
        [GCC_SNOC_USB_CLK] = &gcc_snoc_usb_clk.clkr,
        [GCC_SYS_NOC_AT_CLK] = &gcc_sys_noc_at_clk.clkr,
-       [GCC_SYS_NOC_WCSS_AHB_CLK] = &gcc_sys_noc_wcss_ahb_clk.clkr,
        [GCC_SYSTEM_NOC_BFDCD_CLK_SRC] = &gcc_system_noc_bfdcd_clk_src.clkr,
        [GCC_UNIPHY0_AHB_CLK] = &gcc_uniphy0_ahb_clk.clkr,
        [GCC_UNIPHY0_SYS_CLK] = &gcc_uniphy0_sys_clk.clkr,
@@ -3421,17 +3052,6 @@ static struct clk_regmap *gcc_ipq5332_clocks[] = {
        [GCC_USB0_PIPE_CLK] = &gcc_usb0_pipe_clk.clkr,
        [GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr,
        [GCC_WCSS_AHB_CLK_SRC] = &gcc_wcss_ahb_clk_src.clkr,
-       [GCC_WCSS_AXIM_CLK] = &gcc_wcss_axim_clk.clkr,
-       [GCC_WCSS_AXIS_CLK] = &gcc_wcss_axis_clk.clkr,
-       [GCC_WCSS_DBG_IFC_APB_BDG_CLK] = &gcc_wcss_dbg_ifc_apb_bdg_clk.clkr,
-       [GCC_WCSS_DBG_IFC_APB_CLK] = &gcc_wcss_dbg_ifc_apb_clk.clkr,
-       [GCC_WCSS_DBG_IFC_ATB_BDG_CLK] = &gcc_wcss_dbg_ifc_atb_bdg_clk.clkr,
-       [GCC_WCSS_DBG_IFC_ATB_CLK] = &gcc_wcss_dbg_ifc_atb_clk.clkr,
-       [GCC_WCSS_DBG_IFC_NTS_BDG_CLK] = &gcc_wcss_dbg_ifc_nts_bdg_clk.clkr,
-       [GCC_WCSS_DBG_IFC_NTS_CLK] = &gcc_wcss_dbg_ifc_nts_clk.clkr,
-       [GCC_WCSS_ECAHB_CLK] = &gcc_wcss_ecahb_clk.clkr,
-       [GCC_WCSS_MST_ASYNC_BDG_CLK] = &gcc_wcss_mst_async_bdg_clk.clkr,
-       [GCC_WCSS_SLV_ASYNC_BDG_CLK] = &gcc_wcss_slv_async_bdg_clk.clkr,
        [GCC_XO_CLK] = &gcc_xo_clk.clkr,
        [GCC_XO_CLK_SRC] = &gcc_xo_clk_src.clkr,
        [GCC_XO_DIV4_CLK] = &gcc_xo_div4_clk.clkr,