F: include/linux/irqchip/riscv-aplic.h
F: include/linux/irqchip/riscv-imsic.h
+RISC-V ANDES SoC Support
+M: Ben Zong-You Xie <ben717@andestech.com>
+S: Maintained
+T: git: https://github.com/ben717-linux/linux
+F: Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw.yaml
+F: Documentation/devicetree/bindings/riscv/andes.yaml
+F: Documentation/devicetree/bindings/timer/andestech,plmt0.yaml
+F: arch/riscv/boot/dts/andes/
+
RISC-V ARCHITECTURE
M: Paul Walmsley <paul.walmsley@sifive.com>
M: Palmer Dabbelt <palmer@dabbelt.com>