S/390: Add support for z13 instructions lochi and locghi.

The attached patch adds patterns to make use of the z13 LOCHI and
LOCGHI instructions.

gcc/ChangeLog:

2016-07-04  Dominik Vogt  <vogt@linux.vnet.ibm.com>

	* config/s390/s390.md: Add "z13" cpu_facility.
	("*mov<mode>cc"): Add support for z13 instructions lochi and locghi.
	* config/s390/predicates.md ("loc_operand"): New predicate for "load on
	condition" type instructions.

gcc/testsuite/ChangeLog:

2016-07-04  Dominik Vogt  <vogt@linux.vnet.ibm.com>

	* gcc.target/s390/vector/vec-scalar-cmp-1.c: Expect lochi instead
	of locr.
	* gcc.target/s390/loc-1.c: New test.

From-SVN: r237984

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 2351e896992d9ca5abd903ebc23c6a4e4f2e3c1b..3c1177d5958c6327da4ef736e26daa6e30a96bb6 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2016-07-04  Dominik Vogt  <vogt@linux.vnet.ibm.com>
+
+       * config/s390/s390.md: Add "z13" cpu_facility.
+       ("*mov<mode>cc"): Add support for z13 instructions lochi and locghi.
+       * config/s390/predicates.md ("loc_operand"): New predicate for "load on
+       condition" type instructions.
+
 2016-07-04  Dominik Vogt  <vogt@linux.vnet.ibm.com>
            Jeff Law  <law@redhat.com>
 

diff --git a/gcc/config/s390/predicates.md b/gcc/config/s390/predicates.md
index e66f4a4110b88584238d957de701c7c0f7f7af1c..75e4cb86b20b8c33b20cdf8d9a0ce3876829a87d 100644 (file)
--- a/gcc/config/s390/predicates.md
+++ b/gcc/config/s390/predicates.md
@@ -182,6 +182,13 @@
   return s390_contiguous_bitmask_p (INTVAL (op), GET_MODE_BITSIZE (mode), NULL, NULL);
 })
 
+;; Return true if OP is ligitimate for any LOC instruction.
+
+(define_predicate "loc_operand"
+  (ior (match_operand 0 "nonimmediate_operand")
+      (and (match_code "const_int")
+          (match_test "INTVAL (op) <= 32767 && INTVAL (op) >= -32768"))))
+
 ;; operators --------------------------------------------------------------
 
 ;; Return nonzero if OP is a valid comparison operator

diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index f8c61a8fd063b2d1737b02f004cdacfd51a4496c..6d8d04181ef3a4f0a2be06fb138d67cf5de4883a 100644 (file)
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -483,7 +483,7 @@
   (const (symbol_ref "s390_tune_attr")))
 
 (define_attr "cpu_facility"
-  "standard,ieee,zarch,cpu_zarch,longdisp,extimm,dfp,z10,z196,zEC12,vec"
+  "standard,ieee,zarch,cpu_zarch,longdisp,extimm,dfp,z10,z196,zEC12,vec,z13"
   (const_string "standard"))
 
 (define_attr "enabled" ""
@@ -528,7 +528,12 @@
 
          (and (eq_attr "cpu_facility" "vec")
               (match_test "TARGET_VX"))
-        (const_int 1)]
+        (const_int 1)
+
+         (and (eq_attr "cpu_facility" "z13")
+              (match_test "TARGET_Z13"))
+        (const_int 1)
+        ]
        (const_int 0)))
 
 ;; Pipeline description for z900.  For lack of anything better,
@@ -6309,21 +6314,23 @@
                                     XEXP (operands[1], 1));
 })
 
-; locr, loc, stoc, locgr, locg, stocg
+; locr, loc, stoc, locgr, locg, stocg, lochi, locghi
 (define_insn_and_split "*mov<mode>cc"
-  [(set (match_operand:GPR 0 "nonimmediate_operand"   "=d,d,d,d,S,S,&d")
+  [(set (match_operand:GPR 0 "nonimmediate_operand"   "=d,d,d,d,d,d,S,S,&d")
        (if_then_else:GPR
          (match_operator 1 "s390_comparison"
-           [(match_operand 2 "cc_reg_operand"        " c,c,c,c,c,c,c")
+           [(match_operand 2 "cc_reg_operand"        " c,c,c,c,c,c,c,c,c")
             (match_operand 5 "const_int_operand"     "")])
-         (match_operand:GPR 3 "nonimmediate_operand" " d,0,S,0,d,0,S")
-         (match_operand:GPR 4 "nonimmediate_operand" " 0,d,0,S,0,d,S")))]
+         (match_operand:GPR 3 "loc_operand" " d,0,S,0,K,0,d,0,S")
+         (match_operand:GPR 4 "loc_operand" " 0,d,0,S,0,K,0,d,S")))]
   "TARGET_Z196"
   "@
    loc<g>r%C1\t%0,%3
    loc<g>r%D1\t%0,%4
    loc<g>%C1\t%0,%3
    loc<g>%D1\t%0,%4
+   loc<g>hi%C1\t%0,%h3
+   loc<g>hi%D1\t%0,%h4
    stoc<g>%C1\t%3,%0
    stoc<g>%D1\t%4,%0
    #"
@@ -6340,7 +6347,8 @@
         (match_dup 0)
         (match_dup 4)))]
   ""
-  [(set_attr "op_type" "RRF,RRF,RSY,RSY,RSY,RSY,*")])
+  [(set_attr "op_type" "RRF,RRF,RSY,RSY,RIE,RIE,RSY,RSY,*")
+   (set_attr "cpu_facility" "*,*,*,*,z13,z13,*,*,*")])
 
 ;;
 ;;- Multiply instructions.

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 95d850ae69dac828c0bf4dcf94d01573d656de12..59a437c0421afa87fb8a0f9bc41c51c77c5204b8 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2016-07-04  Dominik Vogt  <vogt@linux.vnet.ibm.com>
+
+       * gcc.target/s390/vector/vec-scalar-cmp-1.c: Expect lochi instead of
+       locr.
+       * gcc.target/s390/loc-1.c: New test.
+
 2016-07-04  Yuri Rumyantsev  <ysrumyan@gmail.com>
 
        * gcc/testsuite/gcc.target/i386/avx512f-vect-perm-1.c: New test.

diff --git a/gcc/testsuite/gcc.target/s390/loc-1.c b/gcc/testsuite/gcc.target/s390/loc-1.c
new file mode 100644 (file)
index 0000000..26dbd9c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/s390/loc-1.c
@@ -0,0 +1,22 @@
+/* Test load on condition patterns.  */
+
+/* { dg-do compile } */
+/* { dg-options "-O3 -march=z13 -mzarch" } */
+
+unsigned long loc_r (unsigned long rc, unsigned long cond, unsigned long val)
+{
+  if (cond)
+    rc = val;
+  return rc;
+}
+/* { dg-final { scan-assembler "\tlocgrne\t%r2,%r4" { target { lp64 } } } } */
+/* { dg-final { scan-assembler "\tlocrne\t%r2,%r4" { target { ! lp64 } } } } */
+
+long loc_hi (long rc, long cond)
+{
+  if (cond)
+    rc = (long)-1;
+  return rc;
+}
+/* { dg-final { scan-assembler "\tlocghine\t%r2,-1" { target { lp64 } } } } */
+/* { dg-final { scan-assembler "\tlochine\t%r2,-1" { target { ! lp64 } } } } */

diff --git a/gcc/testsuite/gcc.target/s390/vector/vec-scalar-cmp-1.c b/gcc/testsuite/gcc.target/s390/vector/vec-scalar-cmp-1.c
index b79120f20f0f7c435a010b1549812f1a1de3cf36..5f63eda4bea0f313cd09aae364f09900a83afe18 100644 (file)
--- a/gcc/testsuite/gcc.target/s390/vector/vec-scalar-cmp-1.c
+++ b/gcc/testsuite/gcc.target/s390/vector/vec-scalar-cmp-1.c
@@ -8,8 +8,8 @@
 /* { dg-final { scan-assembler-times "wfchedbs\t%v\[0-9\]*,%v2,%v0" 1 } } */
 /* { dg-final { scan-assembler-times "wfchdbs\t%v\[0-9\]*,%v2,%v0" 1 } } */
 /* { dg-final { scan-assembler-times "wfchedbs\t%v\[0-9\]*,%v2,%v0" 1 } } */
-/* { dg-final { scan-assembler-times "locrne" 5 } } */
-/* { dg-final { scan-assembler-times "locrno" 1 } } */
+/* { dg-final { scan-assembler-times "lochine" 5 } } */
+/* { dg-final { scan-assembler-times "lochino" 1 } } */
 
 
 int