Check if SSE is available with HAS_CPU_FEATURE

Similar to other CPU feature checks, check if SSE is available with
HAS_CPU_FEATURE.

	* sysdeps/i386/fpu/fclrexcpt.c (__feclearexcept): Use
	HAS_CPU_FEATURE to check for SSE.
	* sysdeps/i386/fpu/fedisblxcpt.c (fedisableexcept): Likewise.
	* sysdeps/i386/fpu/feenablxcpt.c (feenableexcept): Likewise.
	* sysdeps/i386/fpu/fegetenv.c (__fegetenv): Likewise.
	* sysdeps/i386/fpu/fegetmode.c (fegetmode): Likewise.
	* sysdeps/i386/fpu/feholdexcpt.c (__feholdexcept): Likewise.
	* sysdeps/i386/fpu/fesetenv.c (__fesetenv): Likewise.
	* sysdeps/i386/fpu/fesetmode.c (fesetmode): Likewise.
	* sysdeps/i386/fpu/fesetround.c (__fesetround): Likewise.
	* sysdeps/i386/fpu/feupdateenv.c (__feupdateenv): Likewise.
	* sysdeps/i386/fpu/fgetexcptflg.c (__fegetexceptflag): Likewise.
	* sysdeps/i386/fpu/fsetexcptflg.c (__fesetexceptflag): Likewise.
	* sysdeps/i386/fpu/ftestexcept.c (fetestexcept): Likewise.
	* sysdeps/i386/setfpucw.c (__setfpucw): Likewise.
	* sysdeps/x86/cpu-features.h (bit_cpu_SSE): New.
	(index_cpu_SSE): Likewise.
	(reg_SSE): Likewise.

diff --git a/ChangeLog b/ChangeLog
index 848530c231ff165622e65b911c4731ea0182a251..b72d52164e8500930a3ea47612743ac26c6088b9 100644 (file)
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,24 @@
+2017-04-07  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * sysdeps/i386/fpu/fclrexcpt.c (__feclearexcept): Use
+       HAS_CPU_FEATURE to check for SSE.
+       * sysdeps/i386/fpu/fedisblxcpt.c (fedisableexcept): Likewise.
+       * sysdeps/i386/fpu/feenablxcpt.c (feenableexcept): Likewise.
+       * sysdeps/i386/fpu/fegetenv.c (__fegetenv): Likewise.
+       * sysdeps/i386/fpu/fegetmode.c (fegetmode): Likewise.
+       * sysdeps/i386/fpu/feholdexcpt.c (__feholdexcept): Likewise.
+       * sysdeps/i386/fpu/fesetenv.c (__fesetenv): Likewise.
+       * sysdeps/i386/fpu/fesetmode.c (fesetmode): Likewise.
+       * sysdeps/i386/fpu/fesetround.c (__fesetround): Likewise.
+       * sysdeps/i386/fpu/feupdateenv.c (__feupdateenv): Likewise.
+       * sysdeps/i386/fpu/fgetexcptflg.c (__fegetexceptflag): Likewise.
+       * sysdeps/i386/fpu/fsetexcptflg.c (__fesetexceptflag): Likewise.
+       * sysdeps/i386/fpu/ftestexcept.c (fetestexcept): Likewise.
+       * sysdeps/i386/setfpucw.c (__setfpucw): Likewise.
+       * sysdeps/x86/cpu-features.h (bit_cpu_SSE): New.
+       (index_cpu_SSE): Likewise.
+       (reg_SSE): Likewise.
+
 2017-04-07  Paul Eggert  <eggert@cs.ucla.edu>
 
        * posix/getopt1.c: Include <config.h>, not "config.h".

diff --git a/sysdeps/i386/fpu/fclrexcpt.c b/sysdeps/i386/fpu/fclrexcpt.c
index c89fe5bd21ec9d0ce57445b30192f688fdd14ea2..5d8596964b7b242fe88263592d9a7428de698ebe 100644 (file)
--- a/sysdeps/i386/fpu/fclrexcpt.c
+++ b/sysdeps/i386/fpu/fclrexcpt.c
@@ -41,7 +41,7 @@ __feclearexcept (int excepts)
   __asm__ ("fldenv %0" : : "m" (*&temp));
 
   /* If the CPU supports SSE, we clear the MXCSR as well.  */
-  if ((GLRO(dl_hwcap) & HWCAP_I386_XMM) != 0)
+  if (HAS_CPU_FEATURE (SSE))
     {
       unsigned int xnew_exc;
 

diff --git a/sysdeps/i386/fpu/fedisblxcpt.c b/sysdeps/i386/fpu/fedisblxcpt.c
index a12fcafcbc9a61379dfc76a67145e2a634f72dcc..f8db66542577721a10051d6e18e61800385081cf 100644 (file)
--- a/sysdeps/i386/fpu/fedisblxcpt.c
+++ b/sysdeps/i386/fpu/fedisblxcpt.c
@@ -38,7 +38,7 @@ fedisableexcept (int excepts)
   __asm__ ("fldcw %0" : : "m" (*&new_exc));
 
   /* If the CPU supports SSE we set the MXCSR as well.  */
-  if ((GLRO(dl_hwcap) & HWCAP_I386_XMM) != 0)
+  if (HAS_CPU_FEATURE (SSE))
     {
       unsigned int xnew_exc;
 

diff --git a/sysdeps/i386/fpu/feenablxcpt.c b/sysdeps/i386/fpu/feenablxcpt.c
index 8336c1f63dfa036cf858c5423a4937bd0877cfcd..f1c42d7c279abd1cae00952a2a4f5775d77929f9 100644 (file)
--- a/sysdeps/i386/fpu/feenablxcpt.c
+++ b/sysdeps/i386/fpu/feenablxcpt.c
@@ -38,7 +38,7 @@ feenableexcept (int excepts)
   __asm__ ("fldcw %0" : : "m" (*&new_exc));
 
   /* If the CPU supports SSE we set the MXCSR as well.  */
-  if ((GLRO(dl_hwcap) & HWCAP_I386_XMM) != 0)
+  if (HAS_CPU_FEATURE (SSE))
     {
       unsigned int xnew_exc;
 

diff --git a/sysdeps/i386/fpu/fegetenv.c b/sysdeps/i386/fpu/fegetenv.c
index 9ce890eb3c8ffc7e4485b1883c15988388d9d164..983f6af25e14bbb3cd66c1851e3306ed666f2d92 100644 (file)
--- a/sysdeps/i386/fpu/fegetenv.c
+++ b/sysdeps/i386/fpu/fegetenv.c
@@ -31,7 +31,7 @@ __fegetenv (fenv_t *envp)
      would block all exceptions.  */
   __asm__ ("fldenv %0" : : "m" (*envp));
 
-  if ((GLRO(dl_hwcap) & HWCAP_I386_XMM) != 0)
+  if (HAS_CPU_FEATURE (SSE))
     __asm__ ("stmxcsr %0" : "=m" (envp->__eip));
 
   /* Success.  */

diff --git a/sysdeps/i386/fpu/fegetmode.c b/sysdeps/i386/fpu/fegetmode.c
index 3785851aa78d0626315c4a98a430f326ef52ac8e..abbce3075f10152fe954922af602317752ec7151 100644 (file)
--- a/sysdeps/i386/fpu/fegetmode.c
+++ b/sysdeps/i386/fpu/fegetmode.c
@@ -26,7 +26,7 @@ int
 fegetmode (femode_t *modep)
 {
   _FPU_GETCW (modep->__control_word);
-  if ((GLRO(dl_hwcap) & HWCAP_I386_XMM) != 0)
+  if (HAS_CPU_FEATURE (SSE))
     __asm__ ("stmxcsr %0" : "=m" (modep->__mxcsr));
   return 0;
 }

diff --git a/sysdeps/i386/fpu/feholdexcpt.c b/sysdeps/i386/fpu/feholdexcpt.c
index cce883c792042dcd48186f7a2c486ed69cfecaea..d3273589130130f67784a667f42972efe967a6aa 100644 (file)
--- a/sysdeps/i386/fpu/feholdexcpt.c
+++ b/sysdeps/i386/fpu/feholdexcpt.c
@@ -30,7 +30,7 @@ __feholdexcept (fenv_t *envp)
   __asm__ volatile ("fnstenv %0; fnclex" : "=m" (*envp));
 
   /* If the CPU supports SSE we set the MXCSR as well.  */
-  if ((GLRO(dl_hwcap) & HWCAP_I386_XMM) != 0)
+  if (HAS_CPU_FEATURE (SSE))
     {
       unsigned int xwork;
 

diff --git a/sysdeps/i386/fpu/fesetenv.c b/sysdeps/i386/fpu/fesetenv.c
index 18fca30ad54f88bc8c2c2f04265e4804b92e773f..a338e5d5551cf87aec444deaa8dd0df011f0ed33 100644 (file)
--- a/sysdeps/i386/fpu/fesetenv.c
+++ b/sysdeps/i386/fpu/fesetenv.c
@@ -79,7 +79,7 @@ __fesetenv (const fenv_t *envp)
 
   __asm__ ("fldenv %0" : : "m" (temp));
 
-  if ((GLRO(dl_hwcap) & HWCAP_I386_XMM) != 0)
+  if (HAS_CPU_FEATURE (SSE))
     {
       unsigned int mxcsr;
       __asm__ ("stmxcsr %0" : "=m" (mxcsr));

diff --git a/sysdeps/i386/fpu/fesetmode.c b/sysdeps/i386/fpu/fesetmode.c
index 2d038463b7bee55be528ea0a2bb1a8056f3b2693..bd9f74cd975db22771b36710fb6e6f8ff26d84a8 100644 (file)
--- a/sysdeps/i386/fpu/fesetmode.c
+++ b/sysdeps/i386/fpu/fesetmode.c
@@ -35,7 +35,7 @@ fesetmode (const femode_t *modep)
   else
     cw = modep->__control_word;
   _FPU_SETCW (cw);
-  if ((GLRO(dl_hwcap) & HWCAP_I386_XMM) != 0)
+  if (HAS_CPU_FEATURE (SSE))
     {
       unsigned int mxcsr;
       __asm__ ("stmxcsr %0" : "=m" (mxcsr));

diff --git a/sysdeps/i386/fpu/fesetround.c b/sysdeps/i386/fpu/fesetround.c
index fabf0b10389f297ea1d5d690f8eacd50ccb53964..a3fa6235c009393b1c5849b4850aadb2c370fe4b 100644 (file)
--- a/sysdeps/i386/fpu/fesetround.c
+++ b/sysdeps/i386/fpu/fesetround.c
@@ -37,7 +37,7 @@ __fesetround (int round)
   __asm__ ("fldcw %0" : : "m" (*&cw));
 
   /* If the CPU supports SSE we set the MXCSR as well.  */
-  if ((GLRO(dl_hwcap) & HWCAP_I386_XMM) != 0)
+  if (HAS_CPU_FEATURE (SSE))
     {
       unsigned int xcw;
 

diff --git a/sysdeps/i386/fpu/feupdateenv.c b/sysdeps/i386/fpu/feupdateenv.c
index 4b46868ea094cce01a31aa1c553866ea06754ae4..b610289cd0a010d4cc441e1035e996c616d3092c 100644 (file)
--- a/sysdeps/i386/fpu/feupdateenv.c
+++ b/sysdeps/i386/fpu/feupdateenv.c
@@ -32,7 +32,7 @@ __feupdateenv (const fenv_t *envp)
   __asm__ ("fnstsw %0" : "=m" (*&temp));
 
   /* If the CPU supports SSE we test the MXCSR as well.  */
-  if ((GLRO(dl_hwcap) & HWCAP_I386_XMM) != 0)
+  if (HAS_CPU_FEATURE (SSE))
     __asm__ ("stmxcsr %0" : "=m" (*&xtemp));
 
   temp = (temp | xtemp) & FE_ALL_EXCEPT;

diff --git a/sysdeps/i386/fpu/fgetexcptflg.c b/sysdeps/i386/fpu/fgetexcptflg.c
index bf3c73cef12dc203729c173a4f64fd2522082ab6..954e5f69d84d4a17542c4b3e0e644f740cfb3d4d 100644 (file)
--- a/sysdeps/i386/fpu/fgetexcptflg.c
+++ b/sysdeps/i386/fpu/fgetexcptflg.c
@@ -34,7 +34,7 @@ __fegetexceptflag (fexcept_t *flagp, int excepts)
   *flagp = temp & excepts & FE_ALL_EXCEPT;
 
   /* If the CPU supports SSE, we clear the MXCSR as well.  */
-  if ((GLRO(dl_hwcap) & HWCAP_I386_XMM) != 0)
+  if (HAS_CPU_FEATURE (SSE))
     {
       unsigned int sse_exc;
 

diff --git a/sysdeps/i386/fpu/fsetexcptflg.c b/sysdeps/i386/fpu/fsetexcptflg.c
index efea6104fb2df37f41bdf061e824e71bbb9a2c6d..efa64aaefd8885a4f306aa43eede073e5946c6a3 100644 (file)
--- a/sysdeps/i386/fpu/fsetexcptflg.c
+++ b/sysdeps/i386/fpu/fsetexcptflg.c
@@ -41,7 +41,7 @@ __fesetexceptflag (const fexcept_t *flagp, int excepts)
   __asm__ ("fldenv %0" : : "m" (*&temp));
 
   /* If the CPU supports SSE, we set the MXCSR as well.  */
-  if ((GLRO(dl_hwcap) & HWCAP_I386_XMM) != 0)
+  if (HAS_CPU_FEATURE (SSE))
     {
       unsigned int xnew_exc;
 

diff --git a/sysdeps/i386/fpu/ftestexcept.c b/sysdeps/i386/fpu/ftestexcept.c
index 476db1ed62cde7d1c84f10a05cf4ef91445805c3..f523f9e7097dcd8f82d61e4c8180846dd526616a 100644 (file)
--- a/sysdeps/i386/fpu/ftestexcept.c
+++ b/sysdeps/i386/fpu/ftestexcept.c
@@ -32,7 +32,7 @@ fetestexcept (int excepts)
   __asm__ ("fnstsw %0" : "=a" (temp));
 
   /* If the CPU supports SSE we test the MXCSR as well.  */
-  if ((GLRO(dl_hwcap) & HWCAP_I386_XMM) != 0)
+  if (HAS_CPU_FEATURE (SSE))
     __asm__ ("stmxcsr %0" : "=m" (*&xtemp));
 
   return (temp | xtemp) & excepts & FE_ALL_EXCEPT;

diff --git a/sysdeps/i386/setfpucw.c b/sysdeps/i386/setfpucw.c
index 7c414861280766a73aa6c770e5d963ef29713e76..40b995f18a3e43f70ebd694f504a439003bc4e13 100644 (file)
--- a/sysdeps/i386/setfpucw.c
+++ b/sysdeps/i386/setfpucw.c
@@ -39,7 +39,7 @@ __setfpucw (fpu_control_t set)
   __asm__ ("fldcw %0" : : "m" (*&cw));
 
   /* If the CPU supports SSE, we set the MXCSR as well.  */
-  if ((GLRO(dl_hwcap) & HWCAP_I386_XMM) != 0)
+  if (HAS_CPU_FEATURE (SSE))
     {
       unsigned int xnew_exc;
 

diff --git a/sysdeps/x86/cpu-features.h b/sysdeps/x86/cpu-features.h
index 95f0fcff87cb505593b8f5094947e5c024f3b5e8..8ec1562fe7f9b701a590b37bb627734af981c849 100644 (file)
--- a/sysdeps/x86/cpu-features.h
+++ b/sysdeps/x86/cpu-features.h
@@ -45,6 +45,7 @@
 /* COMMON_CPUID_INDEX_1.  */
 #define bit_cpu_CX8            (1 << 8)
 #define bit_cpu_CMOV           (1 << 15)
+#define bit_cpu_SSE            (1 << 25)
 #define bit_cpu_SSE2           (1 << 26)
 #define bit_cpu_SSSE3          (1 << 9)
 #define bit_cpu_SSE4_1         (1 << 19)
@@ -82,6 +83,7 @@
 
 # define index_cpu_CX8 COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_EDX_OFFSET
 # define index_cpu_CMOV        COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_EDX_OFFSET
+# define index_cpu_SSE COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_EDX_OFFSET
 # define index_cpu_SSE2        COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_EDX_OFFSET
 # define index_cpu_SSSE3 COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET
 # define index_cpu_SSE4_1 COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET
@@ -228,6 +230,7 @@ extern const struct cpu_features *__get_cpu_features (void)
 
 # define index_cpu_CX8         COMMON_CPUID_INDEX_1
 # define index_cpu_CMOV                COMMON_CPUID_INDEX_1
+# define index_cpu_SSE         COMMON_CPUID_INDEX_1
 # define index_cpu_SSE2                COMMON_CPUID_INDEX_1
 # define index_cpu_SSSE3       COMMON_CPUID_INDEX_1
 # define index_cpu_SSE4_1      COMMON_CPUID_INDEX_1
@@ -246,6 +249,7 @@ extern const struct cpu_features *__get_cpu_features (void)
 
 # define reg_CX8               edx
 # define reg_CMOV              edx
+# define reg_SSE               edx
 # define reg_SSE2              edx
 # define reg_SSSE3             ecx
 # define reg_SSE4_1            ecx