spi: cadence_qspi: Set tshsl_ns to at least one sclk_ns

tshsl_ns is the clock delay for chip select deassert. This is the delay in
master reference clocks for the length that the master mode chip select
outputs are de-asserted between transactions.

The minimum delay is always SCLK period to ensure the chip select is never
re-asserted within one SCLK period.

That is why tshsl_ns delay should be at least one sclk_ns value. If it is
less than sclk_ns, set it equal to sclk_ns.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20250702065717.3871435-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>

diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index 76569a8019bdfe50832198e89ff9faa8b677fc67..ebfcae9a5b350db034881ecdf0f43b56748d0e78 100644 (file)
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -303,6 +303,10 @@ void cadence_qspi_apb_delay(void *reg_base,
                tshsl_ns -= sclk_ns + ref_clk_ns;
        if (tchsh_ns >= sclk_ns + 3 * ref_clk_ns)
                tchsh_ns -= sclk_ns + 3 * ref_clk_ns;
+
+       if (tshsl_ns < sclk_ns)
+               tshsl_ns = sclk_ns;
+
        tshsl = DIV_ROUND_UP(tshsl_ns, ref_clk_ns);
        tchsh = DIV_ROUND_UP(tchsh_ns, ref_clk_ns);
        tslch = DIV_ROUND_UP(tslch_ns, ref_clk_ns);