re PR target/47246 (Invalid immediate offset for Thumb VFP store regression)

2011-01-26  Chung-Lin Tang  <cltang@codesourcery.com>

	PR target/47246
	* config/arm/arm.c (thumb2_legitimate_index_p): Change the
	lower bound of the allowed Thumb-2 coprocessor load/store
	index range to -256. Add explaining comment.

From-SVN: r169271

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index c26fb8f1e7b5510e21508e7a795a514b8c06dd0e..0997ccea8ac8bc84fd480cb9785f8a9c358ef14e 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2011-01-26  Chung-Lin Tang  <cltang@codesourcery.com>
+
+       PR target/47246
+       * config/arm/arm.c (thumb2_legitimate_index_p): Change the
+       lower bound of the allowed Thumb-2 coprocessor load/store
+       index range to -256. Add explaining comment.
+
 2011-01-25  Ian Lance Taylor  <iant@google.com>
 
        * godump.c (go_define): Improve lexing of macro expansion to only

diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index be09282c17d5e6d12ae93b4e7d4a4cc22c93dc8b..b93756a8ef4a5cbc106d072864bf0225a36fe16f 100644 (file)
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -5786,7 +5786,11 @@ thumb2_legitimate_index_p (enum machine_mode mode, rtx index, int strict_p)
       && (mode == SFmode || mode == DFmode
          || (TARGET_MAVERICK && mode == DImode)))
     return (code == CONST_INT && INTVAL (index) < 1024
-           && INTVAL (index) > -1024
+           /* Thumb-2 allows only > -256 index range for it's core register
+              load/stores. Since we allow SF/DF in core registers, we have
+              to use the intersection between -256~4096 (core) and -1024~1024
+              (coprocessor).  */
+           && INTVAL (index) > -256
            && (INTVAL (index) & 3) == 0);
 
   if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))