remoteproc: mediatek: Setup MT8195 SCP core 1 SRAM offset

Because MT8195 SCP core 0 and core 1 both boot from head of SRAM and
have the same viewpoint of SRAM, SCP has a "core 1 SRAM offset"
configuration to control the access destination of SCP core 1 to boot
core 1 from different SRAM location.

The "core 1 SRAM offset" configuration is composed by a range
and an offset. It works like a simple memory mapped mechanism.
When SCP core 1 accesses a SRAM address located in the range,
the SCP bus adds the configured offset to the address to
shift the physical destination address on SCP SRAM. This shifting is
transparent to the software running on SCP core 1.

Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20230901080935.14571-11-tinghan.shen@mediatek.com
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>

diff --git a/drivers/remoteproc/mtk_common.h b/drivers/remoteproc/mtk_common.h
index fea05bbba9aa4c262d8ef05e49f23754be4ca97c..3d6b53b9f3741a281926f12cc3280ce98269b042 100644 (file)
--- a/drivers/remoteproc/mtk_common.h
+++ b/drivers/remoteproc/mtk_common.h
@@ -65,6 +65,13 @@
 #define MT8195_CORE1_MEM_ATT_PREDEF            0x20008
 #define MT8195_CORE1_WDT_CFG                   0x20034
 
+#define MT8195_SEC_CTRL                                0x85000
+#define MT8195_CORE_OFFSET_ENABLE_D            BIT(13)
+#define MT8195_CORE_OFFSET_ENABLE_I            BIT(12)
+#define MT8195_L2TCM_OFFSET_RANGE_0_LOW                0x850b0
+#define MT8195_L2TCM_OFFSET_RANGE_0_HIGH       0x850b4
+#define MT8195_L2TCM_OFFSET                    0x850d0
+
 #define SCP_FW_VER_LEN                 32
 #define SCP_SHARE_BUFFER_SIZE          288
 

diff --git a/drivers/remoteproc/mtk_scp.c b/drivers/remoteproc/mtk_scp.c
index 6926fd9e4c2e4b9a9db45e0bcfc57ce98b6b426b..2c86695c22c24254e49b1175775e501533f08bf8 100644 (file)
--- a/drivers/remoteproc/mtk_scp.c
+++ b/drivers/remoteproc/mtk_scp.c
@@ -495,6 +495,10 @@ static int mt8195_scp_before_load(struct mtk_scp *scp)
 
 static int mt8195_scp_c1_before_load(struct mtk_scp *scp)
 {
+       u32 sec_ctrl;
+       struct mtk_scp *scp_c0;
+       struct mtk_scp_of_cluster *scp_cluster = scp->cluster;
+
        scp->data->scp_reset_assert(scp);
 
        mt8195_scp_l2tcm_on(scp);
@@ -504,6 +508,30 @@ static int mt8195_scp_c1_before_load(struct mtk_scp *scp)
        /* enable MPU for all memory regions */
        writel(0xff, scp->cluster->reg_base + MT8195_CORE1_MEM_ATT_PREDEF);
 
+       /*
+        * The L2TCM_OFFSET_RANGE and L2TCM_OFFSET shift the destination address
+        * on SRAM when SCP core 1 accesses SRAM.
+        *
+        * This configuration solves booting the SCP core 0 and core 1 from
+        * different SRAM address because core 0 and core 1 both boot from
+        * the head of SRAM by default. this must be configured before boot SCP core 1.
+        *
+        * The value of L2TCM_OFFSET_RANGE is from the viewpoint of SCP core 1.
+        * When SCP core 1 issues address within the range (L2TCM_OFFSET_RANGE),
+        * the address will be added with a fixed offset (L2TCM_OFFSET) on the bus.
+        * The shift action is tranparent to software.
+        */
+       writel(0, scp->cluster->reg_base + MT8195_L2TCM_OFFSET_RANGE_0_LOW);
+       writel(scp->sram_size, scp->cluster->reg_base + MT8195_L2TCM_OFFSET_RANGE_0_HIGH);
+
+       scp_c0 = list_first_entry(&scp_cluster->mtk_scp_list, struct mtk_scp, elem);
+       writel(scp->sram_phys - scp_c0->sram_phys, scp->cluster->reg_base + MT8195_L2TCM_OFFSET);
+
+       /* enable SRAM offset when fetching instruction and data */
+       sec_ctrl = readl(scp->cluster->reg_base + MT8195_SEC_CTRL);
+       sec_ctrl |= MT8195_CORE_OFFSET_ENABLE_I | MT8195_CORE_OFFSET_ENABLE_D;
+       writel(sec_ctrl, scp->cluster->reg_base + MT8195_SEC_CTRL);
+
        return 0;
 }