--- /dev/null
+From d61947a164760ac520cb416768afdf38c33d60e7 Mon Sep 17 00:00:00 2001
+From: Will Deacon <will.deacon@arm.com>
+Date: Thu, 28 Feb 2013 17:46:16 +0100
+Subject: ARM: 7657/1: head: fix swapper and idmap population with LPAE and big-endian
+
+From: Will Deacon <will.deacon@arm.com>
+
+commit d61947a164760ac520cb416768afdf38c33d60e7 upstream.
+
+The LPAE page table format uses 64-bit descriptors, so we need to take
+endianness into account when populating the swapper and idmap tables
+during early initialisation.
+
+This patch ensures that we store the two words making up each page table
+entry in the correct order when running big-endian.
+
+Acked-by: Catalin Marinas <catalin.marinas@arm.com>
+Tested-by: Marc Zyngier <marc.zyngier@arm.com>
+Signed-off-by: Will Deacon <will.deacon@arm.com>
+Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm/kernel/head.S | 26 ++++++++++++++++++++++----
+ 1 file changed, 22 insertions(+), 4 deletions(-)
+
+--- a/arch/arm/kernel/head.S
++++ b/arch/arm/kernel/head.S
+@@ -184,13 +184,22 @@ __create_page_tables:
+ orr r3, r3, #3 @ PGD block type
+ mov r6, #4 @ PTRS_PER_PGD
+ mov r7, #1 << (55 - 32) @ L_PGD_SWAPPER
+-1: str r3, [r0], #4 @ set bottom PGD entry bits
++1:
++#ifdef CONFIG_CPU_ENDIAN_BE8
+ str r7, [r0], #4 @ set top PGD entry bits
++ str r3, [r0], #4 @ set bottom PGD entry bits
++#else
++ str r3, [r0], #4 @ set bottom PGD entry bits
++ str r7, [r0], #4 @ set top PGD entry bits
++#endif
+ add r3, r3, #0x1000 @ next PMD table
+ subs r6, r6, #1
+ bne 1b
+
+ add r4, r4, #0x1000 @ point to the PMD tables
++#ifdef CONFIG_CPU_ENDIAN_BE8
++ add r4, r4, #4 @ we only write the bottom word
++#endif
+ #endif
+
+ ldr r7, [r10, #PROCINFO_MM_MMUFLAGS] @ mm_mmuflags
+@@ -258,6 +267,11 @@ __create_page_tables:
+ addne r6, r6, #1 << SECTION_SHIFT
+ strne r6, [r3]
+
++#if defined(CONFIG_LPAE) && defined(CONFIG_CPU_ENDIAN_BE8)
++ sub r4, r4, #4 @ Fixup page table pointer
++ @ for 64-bit descriptors
++#endif
++
+ #ifdef CONFIG_DEBUG_LL
+ #if !defined(CONFIG_DEBUG_ICEDCC) && !defined(CONFIG_DEBUG_SEMIHOSTING)
+ /*
+@@ -276,13 +290,17 @@ __create_page_tables:
+ orr r3, r7, r3, lsl #SECTION_SHIFT
+ #ifdef CONFIG_ARM_LPAE
+ mov r7, #1 << (54 - 32) @ XN
++#ifdef CONFIG_CPU_ENDIAN_BE8
++ str r7, [r0], #4
++ str r3, [r0], #4
+ #else
+- orr r3, r3, #PMD_SECT_XN
+-#endif
+ str r3, [r0], #4
+-#ifdef CONFIG_ARM_LPAE
+ str r7, [r0], #4
+ #endif
++#else
++ orr r3, r3, #PMD_SECT_XN
++ str r3, [r0], #4
++#endif
+
+ #else /* CONFIG_DEBUG_ICEDCC || CONFIG_DEBUG_SEMIHOSTING */
+ /* we don't need any serial debugging mappings */
--- /dev/null
+From 37f47e3d62533c931b04cb409f2eb299e6342331 Mon Sep 17 00:00:00 2001
+From: Will Deacon <will.deacon@arm.com>
+Date: Thu, 28 Feb 2013 17:47:20 +0100
+Subject: ARM: 7658/1: mm: fix race updating mm->context.id on ASID rollover
+
+From: Will Deacon <will.deacon@arm.com>
+
+commit 37f47e3d62533c931b04cb409f2eb299e6342331 upstream.
+
+If a thread triggers an ASID rollover, other threads of the same process
+must be made to wait until the mm->context.id for the shared mm_struct
+has been updated to new generation and associated book-keeping (e.g.
+TLB invalidation) has ben performed.
+
+However, there is a *tiny* window where both mm->context.id and the
+relevant active_asids entry are updated to the new generation, but the
+TLB flush has not been performed, which could allow another thread to
+return to userspace with a dirty TLB, potentially leading to data
+corruption. In reality this will never occur because one CPU would need
+to perform a context-switch in the time it takes another to do a couple
+of atomic test/set operations but we should plug the race anyway.
+
+This patch moves the active_asids update until after the potential TLB
+flush on context-switch.
+
+Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
+Signed-off-by: Will Deacon <will.deacon@arm.com>
+Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm/mm/context.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+--- a/arch/arm/mm/context.c
++++ b/arch/arm/mm/context.c
+@@ -204,11 +204,11 @@ void check_and_switch_context(struct mm_
+ if ((mm->context.id ^ atomic64_read(&asid_generation)) >> ASID_BITS)
+ new_context(mm, cpu);
+
+- atomic64_set(&per_cpu(active_asids, cpu), mm->context.id);
+- cpumask_set_cpu(cpu, mm_cpumask(mm));
+-
+ if (cpumask_test_and_clear_cpu(cpu, &tlb_flush_pending))
+ local_flush_tlb_all();
++
++ atomic64_set(&per_cpu(active_asids, cpu), mm->context.id);
++ cpumask_set_cpu(cpu, mm_cpumask(mm));
+ raw_spin_unlock_irqrestore(&cpu_asid_lock, flags);
+
+ switch_mm_fastpath:
--- /dev/null
+From 8a4e3a9ead7e37ce1505602b564c15da09ac039f Mon Sep 17 00:00:00 2001
+From: Will Deacon <will.deacon@arm.com>
+Date: Thu, 28 Feb 2013 17:47:36 +0100
+Subject: ARM: 7659/1: mm: make mm->context.id an atomic64_t variable
+
+From: Will Deacon <will.deacon@arm.com>
+
+commit 8a4e3a9ead7e37ce1505602b564c15da09ac039f upstream.
+
+mm->context.id is updated under asid_lock when a new ASID is allocated
+to an mm_struct. However, it is also read without the lock when a task
+is being scheduled and checking whether or not the current ASID
+generation is up-to-date.
+
+If two threads of the same process are being scheduled in parallel and
+the bottom bits of the generation in their mm->context.id match the
+current generation (that is, the mm_struct has not been used for ~2^24
+rollovers) then the non-atomic, lockless access to mm->context.id may
+yield the incorrect ASID.
+
+This patch fixes this issue by making mm->context.id and atomic64_t,
+ensuring that the generation is always read consistently. For code that
+only requires access to the ASID bits (e.g. TLB flushing by mm), then
+the value is accessed directly, which GCC converts to an ldrb.
+
+Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
+Signed-off-by: Will Deacon <will.deacon@arm.com>
+Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm/include/asm/mmu.h | 8 ++++----
+ arch/arm/include/asm/mmu_context.h | 2 +-
+ arch/arm/kernel/asm-offsets.c | 2 +-
+ arch/arm/mm/context.c | 21 +++++++++++++--------
+ 4 files changed, 19 insertions(+), 14 deletions(-)
+
+--- a/arch/arm/include/asm/mmu.h
++++ b/arch/arm/include/asm/mmu.h
+@@ -5,15 +5,15 @@
+
+ typedef struct {
+ #ifdef CONFIG_CPU_HAS_ASID
+- u64 id;
++ atomic64_t id;
+ #endif
+- unsigned int vmalloc_seq;
++ unsigned int vmalloc_seq;
+ } mm_context_t;
+
+ #ifdef CONFIG_CPU_HAS_ASID
+ #define ASID_BITS 8
+ #define ASID_MASK ((~0ULL) << ASID_BITS)
+-#define ASID(mm) ((mm)->context.id & ~ASID_MASK)
++#define ASID(mm) ((mm)->context.id.counter & ~ASID_MASK)
+ #else
+ #define ASID(mm) (0)
+ #endif
+@@ -26,7 +26,7 @@ typedef struct {
+ * modified for 2.6 by Hyok S. Choi <hyok.choi@samsung.com>
+ */
+ typedef struct {
+- unsigned long end_brk;
++ unsigned long end_brk;
+ } mm_context_t;
+
+ #endif
+--- a/arch/arm/include/asm/mmu_context.h
++++ b/arch/arm/include/asm/mmu_context.h
+@@ -25,7 +25,7 @@ void __check_vmalloc_seq(struct mm_struc
+ #ifdef CONFIG_CPU_HAS_ASID
+
+ void check_and_switch_context(struct mm_struct *mm, struct task_struct *tsk);
+-#define init_new_context(tsk,mm) ({ mm->context.id = 0; })
++#define init_new_context(tsk,mm) ({ atomic64_set(&mm->context.id, 0); 0; })
+
+ #else /* !CONFIG_CPU_HAS_ASID */
+
+--- a/arch/arm/kernel/asm-offsets.c
++++ b/arch/arm/kernel/asm-offsets.c
+@@ -107,7 +107,7 @@ int main(void)
+ BLANK();
+ #endif
+ #ifdef CONFIG_CPU_HAS_ASID
+- DEFINE(MM_CONTEXT_ID, offsetof(struct mm_struct, context.id));
++ DEFINE(MM_CONTEXT_ID, offsetof(struct mm_struct, context.id.counter));
+ BLANK();
+ #endif
+ DEFINE(VMA_VM_MM, offsetof(struct vm_area_struct, vm_mm));
+--- a/arch/arm/mm/context.c
++++ b/arch/arm/mm/context.c
+@@ -149,9 +149,9 @@ static int is_reserved_asid(u64 asid)
+ return 0;
+ }
+
+-static void new_context(struct mm_struct *mm, unsigned int cpu)
++static u64 new_context(struct mm_struct *mm, unsigned int cpu)
+ {
+- u64 asid = mm->context.id;
++ u64 asid = atomic64_read(&mm->context.id);
+ u64 generation = atomic64_read(&asid_generation);
+
+ if (asid != 0 && is_reserved_asid(asid)) {
+@@ -178,13 +178,14 @@ static void new_context(struct mm_struct
+ cpumask_clear(mm_cpumask(mm));
+ }
+
+- mm->context.id = asid;
++ return asid;
+ }
+
+ void check_and_switch_context(struct mm_struct *mm, struct task_struct *tsk)
+ {
+ unsigned long flags;
+ unsigned int cpu = smp_processor_id();
++ u64 asid;
+
+ if (unlikely(mm->context.vmalloc_seq != init_mm.context.vmalloc_seq))
+ __check_vmalloc_seq(mm);
+@@ -195,19 +196,23 @@ void check_and_switch_context(struct mm_
+ */
+ cpu_set_reserved_ttbr0();
+
+- if (!((mm->context.id ^ atomic64_read(&asid_generation)) >> ASID_BITS)
+- && atomic64_xchg(&per_cpu(active_asids, cpu), mm->context.id))
++ asid = atomic64_read(&mm->context.id);
++ if (!((asid ^ atomic64_read(&asid_generation)) >> ASID_BITS)
++ && atomic64_xchg(&per_cpu(active_asids, cpu), asid))
+ goto switch_mm_fastpath;
+
+ raw_spin_lock_irqsave(&cpu_asid_lock, flags);
+ /* Check that our ASID belongs to the current generation. */
+- if ((mm->context.id ^ atomic64_read(&asid_generation)) >> ASID_BITS)
+- new_context(mm, cpu);
++ asid = atomic64_read(&mm->context.id);
++ if ((asid ^ atomic64_read(&asid_generation)) >> ASID_BITS) {
++ asid = new_context(mm, cpu);
++ atomic64_set(&mm->context.id, asid);
++ }
+
+ if (cpumask_test_and_clear_cpu(cpu, &tlb_flush_pending))
+ local_flush_tlb_all();
+
+- atomic64_set(&per_cpu(active_asids, cpu), mm->context.id);
++ atomic64_set(&per_cpu(active_asids, cpu), asid);
+ cpumask_set_cpu(cpu, mm_cpumask(mm));
+ raw_spin_unlock_irqrestore(&cpu_asid_lock, flags);
+
--- /dev/null
+From f2fe09b055e2549de41fb107b34c60bac4a1b0cf Mon Sep 17 00:00:00 2001
+From: Will Deacon <will.deacon@arm.com>
+Date: Thu, 28 Feb 2013 17:49:11 +0100
+Subject: ARM: 7663/1: perf: fix ARMv7 EVTYPE_MASK to include NSH bit
+
+From: Will Deacon <will.deacon@arm.com>
+
+commit f2fe09b055e2549de41fb107b34c60bac4a1b0cf upstream.
+
+Masked out PMXEVTYPER.NSH means that we can't enable profiling at PL2,
+regardless of the settings in the HDCR.
+
+This patch fixes the broken mask.
+
+Reported-by: Christoffer Dall <cdall@cs.columbia.edu>
+Signed-off-by: Will Deacon <will.deacon@arm.com>
+Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm/kernel/perf_event_v7.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm/kernel/perf_event_v7.c
++++ b/arch/arm/kernel/perf_event_v7.c
+@@ -774,7 +774,7 @@ static const unsigned armv7_a7_perf_cach
+ /*
+ * PMXEVTYPER: Event selection reg
+ */
+-#define ARMV7_EVTYPE_MASK 0xc00000ff /* Mask for writable bits */
++#define ARMV7_EVTYPE_MASK 0xc80000ff /* Mask for writable bits */
+ #define ARMV7_EVTYPE_EVENT 0xff /* Mask for EVENT bits */
+
+ /*
--- /dev/null
+From 0920a48719f1ceefc909387a64f97563848c7854 Mon Sep 17 00:00:00 2001
+From: Stéphane Marchesin <marcheu@chromium.org>
+Date: Tue, 29 Jan 2013 19:41:59 -0800
+Subject: drm/i915: Increase the RC6p threshold.
+
+From: Stéphane Marchesin <marcheu@chromium.org>
+
+commit 0920a48719f1ceefc909387a64f97563848c7854 upstream.
+
+This increases GEN6_RC6p_THRESHOLD from 100000 to 150000. For some
+reason this avoids the gen6_gt_check_fifodbg.isra warnings and
+associated GPU lockups, which makes my ivy bridge machine stable.
+
+Signed-off-by: Stéphane Marchesin <marcheu@chromium.org>
+Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
+Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/i915/intel_pm.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/i915/intel_pm.c
++++ b/drivers/gpu/drm/i915/intel_pm.c
+@@ -2572,7 +2572,7 @@ static void gen6_enable_rps(struct drm_d
+ I915_WRITE(GEN6_RC_SLEEP, 0);
+ I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
+ I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
+- I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
++ I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
+ I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
+
+ /* Check if we are enabling RC6 */
--- /dev/null
+From e8fc41377f5037ff7a661ea06adc05f1daec1548 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Wed, 27 Feb 2013 12:01:58 -0500
+Subject: drm/radeon: add primary dac adj quirk for R200 board
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit e8fc41377f5037ff7a661ea06adc05f1daec1548 upstream.
+
+vbios values are wrong leading to colors that are
+too bright. Use the default values instead.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/radeon_combios.c | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+--- a/drivers/gpu/drm/radeon/radeon_combios.c
++++ b/drivers/gpu/drm/radeon/radeon_combios.c
+@@ -970,6 +970,15 @@ struct radeon_encoder_primary_dac *radeo
+ found = 1;
+ }
+
++ /* quirks */
++ /* Radeon 9100 (R200) */
++ if ((dev->pdev->device == 0x514D) &&
++ (dev->pdev->subsystem_vendor == 0x174B) &&
++ (dev->pdev->subsystem_device == 0x7149)) {
++ /* vbios value is bad, use the default */
++ found = 0;
++ }
++
+ if (!found) /* fallback to defaults */
+ radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac);
+
--- /dev/null
+From cc9945bf9cac03860b2f7d59882263c965c6e3af Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Tue, 26 Feb 2013 16:17:33 -0500
+Subject: drm/radeon: don't set hpd, afmt interrupts when interrupts are disabled
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit cc9945bf9cac03860b2f7d59882263c965c6e3af upstream.
+
+Avoids splatter if the interrupt handler is not registered due
+to acceleration being disabled.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Jerome Glisse <jglisse@redhat.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/radeon_irq_kms.c | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+--- a/drivers/gpu/drm/radeon/radeon_irq_kms.c
++++ b/drivers/gpu/drm/radeon/radeon_irq_kms.c
+@@ -400,6 +400,9 @@ void radeon_irq_kms_enable_afmt(struct r
+ {
+ unsigned long irqflags;
+
++ if (!rdev->ddev->irq_enabled)
++ return;
++
+ spin_lock_irqsave(&rdev->irq.lock, irqflags);
+ rdev->irq.afmt[block] = true;
+ radeon_irq_set(rdev);
+@@ -419,6 +422,9 @@ void radeon_irq_kms_disable_afmt(struct
+ {
+ unsigned long irqflags;
+
++ if (!rdev->ddev->irq_enabled)
++ return;
++
+ spin_lock_irqsave(&rdev->irq.lock, irqflags);
+ rdev->irq.afmt[block] = false;
+ radeon_irq_set(rdev);
+@@ -438,6 +444,9 @@ void radeon_irq_kms_enable_hpd(struct ra
+ unsigned long irqflags;
+ int i;
+
++ if (!rdev->ddev->irq_enabled)
++ return;
++
+ spin_lock_irqsave(&rdev->irq.lock, irqflags);
+ for (i = 0; i < RADEON_MAX_HPD_PINS; ++i)
+ rdev->irq.hpd[i] |= !!(hpd_mask & (1 << i));
+@@ -458,6 +467,9 @@ void radeon_irq_kms_disable_hpd(struct r
+ unsigned long irqflags;
+ int i;
+
++ if (!rdev->ddev->irq_enabled)
++ return;
++
+ spin_lock_irqsave(&rdev->irq.lock, irqflags);
+ for (i = 0; i < RADEON_MAX_HPD_PINS; ++i)
+ rdev->irq.hpd[i] &= !(hpd_mask & (1 << i));
--- /dev/null
+From dbd712c2272764a536e29ad6841dba74989a39d9 Mon Sep 17 00:00:00 2001
+From: Guenter Roeck <linux@roeck-us.net>
+Date: Thu, 21 Feb 2013 09:33:25 -0800
+Subject: hwmon: (pmbus/ltc2978) Fix peak attribute handling
+
+From: Guenter Roeck <linux@roeck-us.net>
+
+commit dbd712c2272764a536e29ad6841dba74989a39d9 upstream.
+
+Peak attributes were not initialized and cleared correctly.
+Also, temp2_max is only supported on page 0 and thus does not need to be
+an array.
+
+Signed-off-by: Guenter Roeck <linux@roeck-us.net>
+Acked-by: Jean Delvare <khali@linux-fr.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/hwmon/pmbus/ltc2978.c | 28 +++++++++++++++-------------
+ 1 file changed, 15 insertions(+), 13 deletions(-)
+
+--- a/drivers/hwmon/pmbus/ltc2978.c
++++ b/drivers/hwmon/pmbus/ltc2978.c
+@@ -62,7 +62,7 @@ struct ltc2978_data {
+ int temp_min, temp_max;
+ int vout_min[8], vout_max[8];
+ int iout_max[2];
+- int temp2_max[2];
++ int temp2_max;
+ struct pmbus_driver_info info;
+ };
+
+@@ -204,10 +204,9 @@ static int ltc3880_read_word_data(struct
+ ret = pmbus_read_word_data(client, page,
+ LTC3880_MFR_TEMPERATURE2_PEAK);
+ if (ret >= 0) {
+- if (lin11_to_val(ret)
+- > lin11_to_val(data->temp2_max[page]))
+- data->temp2_max[page] = ret;
+- ret = data->temp2_max[page];
++ if (lin11_to_val(ret) > lin11_to_val(data->temp2_max))
++ data->temp2_max = ret;
++ ret = data->temp2_max;
+ }
+ break;
+ case PMBUS_VIRT_READ_VIN_MIN:
+@@ -248,11 +247,11 @@ static int ltc2978_write_word_data(struc
+
+ switch (reg) {
+ case PMBUS_VIRT_RESET_IOUT_HISTORY:
+- data->iout_max[page] = 0x7fff;
++ data->iout_max[page] = 0x7c00;
+ ret = ltc2978_clear_peaks(client, page, data->id);
+ break;
+ case PMBUS_VIRT_RESET_TEMP2_HISTORY:
+- data->temp2_max[page] = 0x7fff;
++ data->temp2_max = 0x7c00;
+ ret = ltc2978_clear_peaks(client, page, data->id);
+ break;
+ case PMBUS_VIRT_RESET_VOUT_HISTORY:
+@@ -262,12 +261,12 @@ static int ltc2978_write_word_data(struc
+ break;
+ case PMBUS_VIRT_RESET_VIN_HISTORY:
+ data->vin_min = 0x7bff;
+- data->vin_max = 0;
++ data->vin_max = 0x7c00;
+ ret = ltc2978_clear_peaks(client, page, data->id);
+ break;
+ case PMBUS_VIRT_RESET_TEMP_HISTORY:
+ data->temp_min = 0x7bff;
+- data->temp_max = 0x7fff;
++ data->temp_max = 0x7c00;
+ ret = ltc2978_clear_peaks(client, page, data->id);
+ break;
+ default:
+@@ -321,10 +320,11 @@ static int ltc2978_probe(struct i2c_clie
+ info = &data->info;
+ info->write_word_data = ltc2978_write_word_data;
+
+- data->vout_min[0] = 0xffff;
+ data->vin_min = 0x7bff;
++ data->vin_max = 0x7c00;
+ data->temp_min = 0x7bff;
+- data->temp_max = 0x7fff;
++ data->temp_max = 0x7c00;
++ data->temp2_max = 0x7c00;
+
+ switch (id->driver_data) {
+ case ltc2978:
+@@ -336,7 +336,6 @@ static int ltc2978_probe(struct i2c_clie
+ for (i = 1; i < 8; i++) {
+ info->func[i] = PMBUS_HAVE_VOUT
+ | PMBUS_HAVE_STATUS_VOUT;
+- data->vout_min[i] = 0xffff;
+ }
+ break;
+ case ltc3880:
+@@ -352,11 +351,14 @@ static int ltc2978_probe(struct i2c_clie
+ | PMBUS_HAVE_IOUT | PMBUS_HAVE_STATUS_IOUT
+ | PMBUS_HAVE_POUT
+ | PMBUS_HAVE_TEMP | PMBUS_HAVE_STATUS_TEMP;
+- data->vout_min[1] = 0xffff;
++ data->iout_max[0] = 0x7c00;
++ data->iout_max[1] = 0x7c00;
+ break;
+ default:
+ return -ENODEV;
+ }
++ for (i = 0; i < info->pages; i++)
++ data->vout_min[i] = 0xffff;
+
+ return pmbus_do_probe(client, id, info);
+ }
--- /dev/null
+From f366fccd0809f13ba20d64cae3c83f7338c88af7 Mon Sep 17 00:00:00 2001
+From: Guenter Roeck <linux@roeck-us.net>
+Date: Thu, 21 Feb 2013 10:49:40 -0800
+Subject: hwmon: (pmbus/ltc2978) Use detected chip ID to select supported functionality
+
+From: Guenter Roeck <linux@roeck-us.net>
+
+commit f366fccd0809f13ba20d64cae3c83f7338c88af7 upstream.
+
+We read the chip ID from the chip, use it to determine if the chip ID provided
+to the driver is correct, and report it if wrong. We should also use the
+correct chip ID to select supported functionality.
+
+Signed-off-by: Guenter Roeck <linux@roeck-us.net>
+Acked-by: Jean Delvare <khali@linux-fr.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/hwmon/pmbus/ltc2978.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/hwmon/pmbus/ltc2978.c
++++ b/drivers/hwmon/pmbus/ltc2978.c
+@@ -326,7 +326,7 @@ static int ltc2978_probe(struct i2c_clie
+ data->temp_max = 0x7c00;
+ data->temp2_max = 0x7c00;
+
+- switch (id->driver_data) {
++ switch (data->id) {
+ case ltc2978:
+ info->read_word_data = ltc2978_read_word_data;
+ info->pages = 8;
--- /dev/null
+From 3e78080f81481aa8340374d5a37ae033c1cf4272 Mon Sep 17 00:00:00 2001
+From: Mark Brown <broonie@opensource.wolfsonmicro.com>
+Date: Sat, 2 Mar 2013 15:33:30 +0800
+Subject: hwmon: (sht15) Check return value of regulator_enable()
+
+From: Mark Brown <broonie@opensource.wolfsonmicro.com>
+
+commit 3e78080f81481aa8340374d5a37ae033c1cf4272 upstream.
+
+Not having power is a pretty serious error so check that we are able to
+enable the supply and error out if we can't.
+
+Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
+Signed-off-by: Guenter Roeck <linux@roeck-us.net>
+
+---
+ drivers/hwmon/sht15.c | 8 +++++++-
+ 1 file changed, 7 insertions(+), 1 deletion(-)
+
+--- a/drivers/hwmon/sht15.c
++++ b/drivers/hwmon/sht15.c
+@@ -926,7 +926,13 @@ static int sht15_probe(struct platform_d
+ if (voltage)
+ data->supply_uV = voltage;
+
+- regulator_enable(data->reg);
++ ret = regulator_enable(data->reg);
++ if (ret != 0) {
++ dev_err(&pdev->dev,
++ "failed to enable regulator: %d\n", ret);
++ return ret;
++ }
++
+ /*
+ * Setup a notifier block to update this if another device
+ * causes the voltage to change
md-fix-two-bugs-when-attempting-to-resize-raid0-array.patch
md-raid0-fix-error-return-from-create_stripe_zones.patch
md-raid1-raid10-fix-deadlock-with-freeze_array.patch
+hwmon-sht15-check-return-value-of-regulator_enable.patch
+hwmon-pmbus-ltc2978-fix-peak-attribute-handling.patch
+hwmon-pmbus-ltc2978-use-detected-chip-id-to-select.patch
+drm-radeon-don-t-set-hpd-afmt-interrupts-when-interrupts-are-disabled.patch
+drm-radeon-add-primary-dac-adj-quirk-for-r200-board.patch
+arm-7657-1-head-fix-swapper-and-idmap-population-with-lpae-and-big-endian.patch
+arm-7658-1-mm-fix-race-updating-mm-context.id-on-asid-rollover.patch
+arm-7659-1-mm-make-mm-context.id-an-atomic64_t-variable.patch
+arm-7663-1-perf-fix-armv7-evtype_mask-to-include-nsh-bit.patch
+drm-i915-increase-the-rc6p-threshold.patch
projects / thirdparty / kernel / stable-queue.git / commitdiff
