iommu/arm-smmu-v3: Shrink the cdtab l1_desc array

The top of the 2 level CD table is (at most) 1024 entries big, and two
high order allocations are required. One of __le64 which is programmed
into the HW (8k) and one of struct arm_smmu_l1_ctx_desc which holds the
CPU pointer (16k).

There are two copies of the l2ptr_dma, one is stored in the struct
arm_smmu_l1_ctx_desc, and another is encoded in the __le64 for the HW to
use. Instead of storing two copies just decode the value from the __le64.

Tested-by: Nicolin Chen <nicolinc@nvidia.com>
Reviewed-by: Nicolin Chen <nicolinc@nvidia.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
Link: https://lore.kernel.org/r/6-v4-6416877274e1+1af-smmuv3_tidy_jgg@nvidia.com
Signed-off-by: Will Deacon <will@kernel.org>

diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
index c69d50e39b21eb2109591b0fe25dea6063e4a881..3c33ebffbe62de764825bb47b0c7cc315698e8cd 100644 (file)
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
@@ -1217,29 +1217,17 @@ static void arm_smmu_sync_cd(struct arm_smmu_master *master,
        arm_smmu_cmdq_batch_submit(smmu, &cmds);
 }
 
-static int arm_smmu_alloc_cd_leaf_table(struct arm_smmu_device *smmu,
-                                       struct arm_smmu_l1_ctx_desc *l1_desc)
+static void arm_smmu_write_cd_l1_desc(__le64 *dst, dma_addr_t l2ptr_dma)
 {
-       size_t size = CTXDESC_L2_ENTRIES * (CTXDESC_CD_DWORDS << 3);
+       u64 val = (l2ptr_dma & CTXDESC_L1_DESC_L2PTR_MASK) | CTXDESC_L1_DESC_V;
 
-       l1_desc->l2ptr = dma_alloc_coherent(smmu->dev, size,
-                                           &l1_desc->l2ptr_dma, GFP_KERNEL);
-       if (!l1_desc->l2ptr) {
-               dev_warn(smmu->dev,
-                        "failed to allocate context descriptor table\n");
-               return -ENOMEM;
-       }
-       return 0;
+       /* The HW has 64 bit atomicity with stores to the L2 CD table */
+       WRITE_ONCE(*dst, cpu_to_le64(val));
 }
 
-static void arm_smmu_write_cd_l1_desc(__le64 *dst,
-                                     struct arm_smmu_l1_ctx_desc *l1_desc)
+static dma_addr_t arm_smmu_cd_l1_get_desc(const __le64 *src)
 {
-       u64 val = (l1_desc->l2ptr_dma & CTXDESC_L1_DESC_L2PTR_MASK) |
-                 CTXDESC_L1_DESC_V;
-
-       /* The HW has 64 bit atomicity with stores to the L2 CD table */
-       WRITE_ONCE(*dst, cpu_to_le64(val));
+       return le64_to_cpu(*src) & CTXDESC_L1_DESC_L2PTR_MASK;
 }
 
 struct arm_smmu_cd *arm_smmu_get_cd_ptr(struct arm_smmu_master *master,
@@ -1281,13 +1269,18 @@ static struct arm_smmu_cd *arm_smmu_alloc_cd_ptr(struct arm_smmu_master *master,
 
                l1_desc = &cd_table->l1_desc[idx];
                if (!l1_desc->l2ptr) {
-                       __le64 *l1ptr;
-
-                       if (arm_smmu_alloc_cd_leaf_table(smmu, l1_desc))
+                       dma_addr_t l2ptr_dma;
+                       size_t size;
+
+                       size = CTXDESC_L2_ENTRIES * sizeof(struct arm_smmu_cd);
+                       l1_desc->l2ptr = dma_alloc_coherent(smmu->dev, size,
+                                                           &l2ptr_dma,
+                                                           GFP_KERNEL);
+                       if (!l1_desc->l2ptr)
                                return NULL;
 
-                       l1ptr = cd_table->cdtab + idx * CTXDESC_L1_DESC_DWORDS;
-                       arm_smmu_write_cd_l1_desc(l1ptr, l1_desc);
+                       arm_smmu_write_cd_l1_desc(&cd_table->cdtab[idx],
+                                                 l2ptr_dma);
                        /* An invalid L1CD can be cached */
                        arm_smmu_sync_cd(master, ssid, false);
                }
@@ -1480,7 +1473,8 @@ static void arm_smmu_free_cd_tables(struct arm_smmu_master *master)
 
                        dma_free_coherent(smmu->dev, size,
                                          cd_table->l1_desc[i].l2ptr,
-                                         cd_table->l1_desc[i].l2ptr_dma);
+                                         arm_smmu_cd_l1_get_desc(
+                                                 &cd_table->cdtab[i]));
                }
                kfree(cd_table->l1_desc);
 

diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
index 33a8bee1b82e3b7c162913f759f8583c133b7fbf..8b5628771b9671bcd43be4c8b4caa566727e22f8 100644 (file)
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
@@ -619,7 +619,6 @@ struct arm_smmu_ctx_desc {
 
 struct arm_smmu_l1_ctx_desc {
        struct arm_smmu_cd              *l2ptr;
-       dma_addr_t                      l2ptr_dma;
 };
 
 struct arm_smmu_ctx_desc_cfg {