PCI: dw-rockchip: Delay link training after hot reset in EP mode

RK3588 TRM, section "11.6.1.3.3 Hot Reset and Link-Down Reset" states that:

  If you want to delay link re-establishment (after reset) so that you can
  reprogram some registers through DBI, you must set app_ltssm_enable =0
  immediately after core_rst_n as shown in above. This can be achieved by
  enable the app_dly2_en, and end-up the delay by assert app_dly2_done.

I.e. setting app_dly2_en will automatically deassert app_ltssm_enable on
a hot reset, and setting app_dly2_done will re-assert app_ltssm_enable,
re-enabling link training.

When receiving a hot reset/link-down IRQ when running in EP mode, we will
call dw_pcie_ep_linkdown(), which may update registers through DBI. Unless
link training is inhibited, these register updates race with the link
training.

To avoid the race, set PCIE_LTSSM_APP_DLY2_EN so the controller never
automatically trains the link after a link-down or hot reset interrupt.
That way any DBI updates done in the dw_pcie_ep_linkdown() path will happen
while the link is still down.  Then allow link training by setting
PCIE_LTSSM_APP_DLY2_DONE

Co-developed-by: Niklas Cassel <cassel@kernel.org>
Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Signed-off-by: Niklas Cassel <cassel@kernel.org>
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
[bhelgaas: commit log]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://patch.msgid.link/20250613101908.2182053-2-cassel@kernel.org

diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
index 93171a3928794915ad1e8c03c017ce0afc1f9169..cd1e9352b21fcabca0bb241366012f9bd716e17b 100644 (file)
--- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
+++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
@@ -58,6 +58,8 @@
 
 /* Hot Reset Control Register */
 #define PCIE_CLIENT_HOT_RESET_CTRL     0x180
+#define  PCIE_LTSSM_APP_DLY2_EN                BIT(1)
+#define  PCIE_LTSSM_APP_DLY2_DONE      BIT(3)
 #define  PCIE_LTSSM_ENABLE_ENHANCE     BIT(4)
 
 /* LTSSM Status Register */
@@ -474,7 +476,7 @@ static irqreturn_t rockchip_pcie_ep_sys_irq_thread(int irq, void *arg)
        struct rockchip_pcie *rockchip = arg;
        struct dw_pcie *pci = &rockchip->pci;
        struct device *dev = pci->dev;
-       u32 reg;
+       u32 reg, val;
 
        reg = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_INTR_STATUS_MISC);
        rockchip_pcie_writel_apb(rockchip, reg, PCIE_CLIENT_INTR_STATUS_MISC);
@@ -485,6 +487,10 @@ static irqreturn_t rockchip_pcie_ep_sys_irq_thread(int irq, void *arg)
        if (reg & PCIE_LINK_REQ_RST_NOT_INT) {
                dev_dbg(dev, "hot reset or link-down reset\n");
                dw_pcie_ep_linkdown(&pci->ep);
+               /* Stop delaying link training. */
+               val = HIWORD_UPDATE_BIT(PCIE_LTSSM_APP_DLY2_DONE);
+               rockchip_pcie_writel_apb(rockchip, val,
+                                        PCIE_CLIENT_HOT_RESET_CTRL);
        }
 
        if (reg & PCIE_RDLH_LINK_UP_CHGED) {
@@ -566,8 +572,11 @@ static int rockchip_pcie_configure_ep(struct platform_device *pdev,
                return ret;
        }
 
-       /* LTSSM enable control mode */
-       val = HIWORD_UPDATE_BIT(PCIE_LTSSM_ENABLE_ENHANCE);
+       /*
+        * LTSSM enable control mode, and automatically delay link training on
+        * hot reset/link-down reset.
+        */
+       val = HIWORD_UPDATE_BIT(PCIE_LTSSM_ENABLE_ENHANCE | PCIE_LTSSM_APP_DLY2_EN);
        rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL);
 
        rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_EP_MODE,