PCI: Add PCIe Device 3 Extended Capability enumeration

PCIe r7.0 Section 7.7.9 Device 3 Extended Capability Structure, defines the
canonical location for determining the Flit Mode of a device. This status
is a dependency for PCIe IDE enabling. Add a new fm_enabled flag to 'struct
pci_dev'.

Cc: Lukas Wunner <lukas@wunner.de>
Cc: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Samuel Ortiz <sameo@rivosinc.com>
Cc: Alexey Kardashevskiy <aik@amd.com>
Cc: Xu Yilun <yilun.xu@linux.intel.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Link: https://patch.msgid.link/20251031212902.2256310-6-dan.j.williams@intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>

diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index d1467348c169906ef0fd020f9dfd80df60719902..3b54f1720be5759f71d0e114b202c4c70e571ef3 100644 (file)
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -2283,6 +2283,17 @@ int pci_configure_extended_tags(struct pci_dev *dev, void *ign)
        return 0;
 }
 
+static void pci_dev3_init(struct pci_dev *pdev)
+{
+       u16 cap = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_DEV3);
+       u32 val = 0;
+
+       if (!cap)
+               return;
+       pci_read_config_dword(pdev, cap + PCI_DEV3_STA, &val);
+       pdev->fm_enabled = !!(val & PCI_DEV3_STA_SEGMENT);
+}
+
 /**
  * pcie_relaxed_ordering_enabled - Probe for PCIe relaxed ordering enable
  * @dev: PCI device to query
@@ -2667,6 +2678,7 @@ static void pci_init_capabilities(struct pci_dev *dev)
        pci_doe_init(dev);              /* Data Object Exchange */
        pci_tph_init(dev);              /* TLP Processing Hints */
        pci_rebar_init(dev);            /* Resizable BAR */
+       pci_dev3_init(dev);             /* Device 3 capabilities */
        pci_ide_init(dev);              /* Link Integrity and Data Encryption */
 
        pcie_report_downtraining(dev);

diff --git a/include/linux/pci.h b/include/linux/pci.h
index 2f9c0cb6a50a0ea592ab7a4394efb3357fe7226c..ea94799c81b0d91313d4c0b086628054bdf593f3 100644 (file)
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -450,6 +450,7 @@ struct pci_dev {
        unsigned int    pasid_enabled:1;        /* Process Address Space ID */
        unsigned int    pri_enabled:1;          /* Page Request Interface */
        unsigned int    tph_enabled:1;          /* TLP Processing Hints */
+       unsigned int    fm_enabled:1;           /* Flit Mode (segment captured) */
        unsigned int    is_managed:1;           /* Managed via devres */
        unsigned int    is_msi_managed:1;       /* MSI release via devres installed */
        unsigned int    needs_freset:1;         /* Requires fundamental reset */

diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index f2759c1097bcefb64b26441bce1e1d39b2e1c4e7..3add74ae259483bab76e7552cb28bd9c9ef0b30c 100644 (file)
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -755,6 +755,7 @@
 #define PCI_EXT_CAP_ID_NPEM    0x29    /* Native PCIe Enclosure Management */
 #define PCI_EXT_CAP_ID_PL_32GT  0x2A    /* Physical Layer 32.0 GT/s */
 #define PCI_EXT_CAP_ID_DOE     0x2E    /* Data Object Exchange */
+#define PCI_EXT_CAP_ID_DEV3    0x2F    /* Device 3 Capability/Control/Status */
 #define PCI_EXT_CAP_ID_IDE     0x30    /* Integrity and Data Encryption */
 #define PCI_EXT_CAP_ID_PL_64GT 0x31    /* Physical Layer 64.0 GT/s */
 #define PCI_EXT_CAP_ID_MAX     PCI_EXT_CAP_ID_PL_64GT
@@ -1246,6 +1247,12 @@
 /* Deprecated old name, replaced with PCI_DOE_DATA_OBJECT_DISC_RSP_3_TYPE */
 #define PCI_DOE_DATA_OBJECT_DISC_RSP_3_PROTOCOL                PCI_DOE_DATA_OBJECT_DISC_RSP_3_TYPE
 
+/* Device 3 Extended Capability */
+#define PCI_DEV3_CAP           0x04    /* Device 3 Capabilities Register */
+#define PCI_DEV3_CTL           0x08    /* Device 3 Control Register */
+#define PCI_DEV3_STA           0x0c    /* Device 3 Status Register */
+#define  PCI_DEV3_STA_SEGMENT  0x8     /* Segment Captured (end-to-end flit-mode detected) */
+
 /* Compute Express Link (CXL r3.1, sec 8.1.5) */
 #define PCI_DVSEC_CXL_PORT                             3
 #define PCI_DVSEC_CXL_PORT_CTL                         0x0c