#define STM32_GPIO_AFRL 0x20
#define STM32_GPIO_AFRH 0x24
#define STM32_GPIO_SECCFGR 0x30
+#define STM32_GPIO_DELAYRL 0x40
+#define STM32_GPIO_ADVCFGRL 0x48
#define STM32_GPIO_CIDCFGR(x) (0x50 + (0x8 * (x)))
#define STM32_GPIO_SEMCR(x) (0x54 + (0x8 * (x)))
+/* Unitary delay for STM32_GPIO_DELAYRL */
+#define STM32_GPIO_DELAYRL_PS 250
+
+#define STM32_GPIO_ADVCFGR_DLYPATH_MASK BIT(0)
+#define STM32_GPIO_ADVCFGR_DE_MASK BIT(1)
+#define STM32_GPIO_ADVCFGR_INVCLK_MASK BIT(2)
+#define STM32_GPIO_ADVCFGR_RET_MASK BIT(3)
+#define STM32_GPIO_ADVCFGR_IO_SYNC_MASK \
+ (STM32_GPIO_ADVCFGR_DE_MASK \
+ | STM32_GPIO_ADVCFGR_INVCLK_MASK \
+ | STM32_GPIO_ADVCFGR_RET_MASK)
+
#define STM32_GPIO_CIDCFGR_CFEN BIT(0)
#define STM32_GPIO_CIDCFGR_SEMEN BIT(1)
#define STM32_GPIO_CIDCFGR_SCID_MASK GENMASK(5, 4)
#define SYSCFG_IRQMUX_MASK GENMASK(3, 0)
+/* Vendor specific pin configuration */
+#define STM32_GPIO_PIN_CONFIG_IO_SYNC (PIN_CONFIG_END + 1)
+
#define gpio_range_to_bank(chip) \
container_of(chip, struct stm32_gpio_bank, range)
"reserved",
};
+static const char * const stm32_gpio_io_sync[] = {
+ "pass-through",
+ "clock inverted",
+ "data on rising edge",
+ "data on falling edge",
+ "data on both edges",
+};
+
+static u8 io_sync_2_advcfgr[] = {
+ /* data or clock GPIO pass-through */
+ [0] = 0,
+ /* clock GPIO inverted */
+ [1] = STM32_GPIO_ADVCFGR_INVCLK_MASK,
+ /* data GPIO re-sampled on clock rising edge */
+ [2] = STM32_GPIO_ADVCFGR_RET_MASK,
+ /* data GPIO re-sampled on clock falling edge */
+ [3] = STM32_GPIO_ADVCFGR_RET_MASK | STM32_GPIO_ADVCFGR_INVCLK_MASK,
+ /* data GPIO re-sampled on both clock edges */
+ [4] = STM32_GPIO_ADVCFGR_RET_MASK | STM32_GPIO_ADVCFGR_DE_MASK,
+};
+
+static const struct pinconf_generic_params stm32_gpio_bindings[] = {
+ {"st,io-sync", STM32_GPIO_PIN_CONFIG_IO_SYNC, 0,
+ stm32_gpio_io_sync, ARRAY_SIZE(stm32_gpio_io_sync)},
+};
+
struct stm32_pinctrl_group {
const char *name;
unsigned long config;
unsigned int speed:2;
unsigned int drive:1;
unsigned int value:1;
+ unsigned int advcfg:4;
+ unsigned int skew_delay:4;
};
struct stm32_gpio_bank {
struct stm32_pin_backup pin_backup[STM32_GPIO_PINS_PER_BANK];
u8 irq_type[STM32_GPIO_PINS_PER_BANK];
bool secure_control;
+ bool io_sync_control;
bool rif_control;
};
bank->pin_backup[offset].bias = bias;
}
+static void stm32_gpio_backup_advcfg(struct stm32_gpio_bank *bank, u32 offset, u32 mask, u32 value)
+{
+ u32 val;
+
+ val = bank->pin_backup[offset].advcfg;
+ val &= ~mask;
+ val |= value & mask;
+ bank->pin_backup[offset].advcfg = val;
+}
+
+static void stm32_gpio_backup_skew_delay(struct stm32_gpio_bank *bank, u32 offset, u32 delay)
+{
+ bank->pin_backup[offset].skew_delay = delay;
+}
+
/* RIF functions */
static bool stm32_gpio_rif_valid(struct stm32_gpio_bank *bank, unsigned int gpio_nr)
return (val >> (offset * 2));
}
+static void
+stm32_pconf_set_advcfgr_nolock(struct stm32_gpio_bank *bank, int offset, u32 mask, u32 value)
+{
+ int advcfgr_offset = STM32_GPIO_ADVCFGRL + (offset / 8) * 4;
+ int advcfgr_shift = (offset % 8) * 4;
+ u32 val;
+
+ val = readl_relaxed(bank->base + advcfgr_offset);
+ val &= ~(mask << advcfgr_shift);
+ val |= (value & mask) << advcfgr_shift;
+ writel_relaxed(val, bank->base + advcfgr_offset);
+
+ stm32_gpio_backup_advcfg(bank, offset, mask, value);
+}
+
+static int stm32_pconf_set_advcfgr(struct stm32_gpio_bank *bank, int offset, u32 mask, u32 value)
+{
+ struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
+ unsigned long flags;
+ int err = 0;
+
+ if (!bank->io_sync_control)
+ return -ENOTSUPP;
+
+ spin_lock_irqsave(&bank->lock, flags);
+
+ if (pctl->hwlock) {
+ err = hwspin_lock_timeout_in_atomic(pctl->hwlock, HWSPNLCK_TIMEOUT);
+ if (err) {
+ dev_err(pctl->dev, "Can't get hwspinlock\n");
+ goto unlock;
+ }
+ }
+
+ stm32_pconf_set_advcfgr_nolock(bank, offset, mask, value);
+
+ if (pctl->hwlock)
+ hwspin_unlock_in_atomic(pctl->hwlock);
+
+unlock:
+ spin_unlock_irqrestore(&bank->lock, flags);
+
+ return err;
+}
+
+static u32 stm32_pconf_get_advcfgr(struct stm32_gpio_bank *bank, int offset, u32 mask)
+{
+ int advcfgr_offset = STM32_GPIO_ADVCFGRL + (offset / 8) * 4;
+ int advcfgr_shift = (offset % 8) * 4;
+ u32 val;
+
+ if (!bank->io_sync_control)
+ return 0;
+
+ val = readl_relaxed(bank->base + advcfgr_offset);
+ val >>= advcfgr_shift;
+
+ return val & mask;
+}
+
+static int stm32_pconf_set_io_sync(struct stm32_gpio_bank *bank, int offset, u32 io_sync)
+{
+ if (io_sync >= ARRAY_SIZE(io_sync_2_advcfgr))
+ return -EINVAL;
+
+ return stm32_pconf_set_advcfgr(bank, offset, STM32_GPIO_ADVCFGR_IO_SYNC_MASK,
+ io_sync_2_advcfgr[io_sync]);
+}
+
+static const char *stm32_pconf_get_io_sync_str(struct stm32_gpio_bank *bank, int offset)
+{
+ u32 io_sync = stm32_pconf_get_advcfgr(bank, offset, STM32_GPIO_ADVCFGR_IO_SYNC_MASK);
+
+ if (io_sync & STM32_GPIO_ADVCFGR_RET_MASK) {
+ if (io_sync & STM32_GPIO_ADVCFGR_DE_MASK)
+ return "data GPIO re-sampled on both clock edges";
+
+ if (io_sync & STM32_GPIO_ADVCFGR_INVCLK_MASK)
+ return "data GPIO re-sampled on clock falling edge";
+
+ return "data GPIO re-sampled on clock rising edge";
+ }
+
+ if (io_sync & STM32_GPIO_ADVCFGR_INVCLK_MASK)
+ return "clock GPIO inverted";
+
+ return NULL;
+}
+
+static int
+stm32_pconf_set_skew_delay(struct stm32_gpio_bank *bank, int offset, u32 delay, bool is_dir_input)
+{
+ struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
+ int delay_offset = STM32_GPIO_DELAYRL + (offset / 8) * 4;
+ int delay_shift = (offset % 8) * 4;
+ unsigned long flags;
+ int err = 0;
+ u32 val;
+
+ if (!bank->io_sync_control)
+ return -ENOTSUPP;
+
+ spin_lock_irqsave(&bank->lock, flags);
+
+ if (pctl->hwlock) {
+ err = hwspin_lock_timeout_in_atomic(pctl->hwlock, HWSPNLCK_TIMEOUT);
+ if (err) {
+ dev_err(pctl->dev, "Can't get hwspinlock\n");
+ goto unlock;
+ }
+ }
+
+ val = readl_relaxed(bank->base + delay_offset);
+ val &= ~GENMASK(delay_shift + 3, delay_shift);
+ val |= (delay << delay_shift);
+ writel_relaxed(val, bank->base + delay_offset);
+
+ stm32_gpio_backup_skew_delay(bank, offset, delay);
+
+ stm32_pconf_set_advcfgr_nolock(bank, offset, STM32_GPIO_ADVCFGR_DLYPATH_MASK,
+ is_dir_input ? STM32_GPIO_ADVCFGR_DLYPATH_MASK : 0);
+
+ if (pctl->hwlock)
+ hwspin_unlock_in_atomic(pctl->hwlock);
+
+unlock:
+ spin_unlock_irqrestore(&bank->lock, flags);
+
+ return err;
+}
+
+static u32 stm32_pconf_get_skew_delay_val(struct stm32_gpio_bank *bank, int offset)
+{
+ int delay_offset = STM32_GPIO_DELAYRL + (offset / 8) * 4;
+ int delay_shift = (offset % 8) * 4;
+ u32 val;
+
+ val = readl_relaxed(bank->base + delay_offset);
+ val &= GENMASK(delay_shift + 3, delay_shift);
+
+ return val >> delay_shift;
+}
+
+static const char *stm32_pconf_get_skew_dir_str(struct stm32_gpio_bank *bank, int offset)
+{
+ return stm32_pconf_get_advcfgr(bank, offset, STM32_GPIO_ADVCFGR_DLYPATH_MASK) ?
+ "input" : "output";
+}
+
static bool stm32_pconf_get(struct stm32_gpio_bank *bank,
unsigned int offset, bool dir)
{
__stm32_gpio_set(bank, offset, arg);
ret = stm32_pmx_gpio_set_direction(pctldev, range, pin, false);
break;
+ case PIN_CONFIG_SKEW_DELAY_INPUT_PS:
+ arg /= STM32_GPIO_DELAYRL_PS;
+ ret = stm32_pconf_set_skew_delay(bank, offset, arg, true);
+ break;
+ case PIN_CONFIG_SKEW_DELAY_OUTPUT_PS:
+ arg /= STM32_GPIO_DELAYRL_PS;
+ ret = stm32_pconf_set_skew_delay(bank, offset, arg, false);
+ break;
+ case STM32_GPIO_PIN_CONFIG_IO_SYNC:
+ ret = stm32_pconf_set_io_sync(bank, offset, arg);
+ break;
default:
ret = -ENOTSUPP;
}
case 3:
break;
}
+
+ if (bank->io_sync_control) {
+ const char *io_sync_str, *skew_dir_str;
+ u32 skew_delay;
+
+ io_sync_str = stm32_pconf_get_io_sync_str(bank, offset);
+ skew_dir_str = stm32_pconf_get_skew_dir_str(bank, offset);
+ skew_delay = stm32_pconf_get_skew_delay_val(bank, offset);
+
+ if (io_sync_str)
+ seq_printf(s, " - IO-sync: %s", io_sync_str);
+
+ if (skew_delay)
+ seq_printf(s, " - Skew-delay: %u (%u ps) %s", skew_delay,
+ skew_delay * STM32_GPIO_DELAYRL_PS, skew_dir_str);
+ }
}
static const struct pinconf_ops stm32_pconf_ops = {
bank->bank_nr = bank_nr;
bank->bank_ioport_nr = bank_ioport_nr;
bank->secure_control = pctl->match_data->secure_control;
+ bank->io_sync_control = pctl->match_data->io_sync_control;
bank->rif_control = pctl->match_data->rif_control;
spin_lock_init(&bank->lock);
pctl->pctl_desc.confops = &stm32_pconf_ops;
pctl->pctl_desc.pctlops = &stm32_pctrl_ops;
pctl->pctl_desc.pmxops = &stm32_pmx_ops;
+ pctl->pctl_desc.num_custom_params = ARRAY_SIZE(stm32_gpio_bindings);
+ pctl->pctl_desc.custom_params = stm32_gpio_bindings;
pctl->dev = &pdev->dev;
pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc,
if (ret)
return ret;
+ if (bank->io_sync_control) {
+ bool is_input = bank->pin_backup[offset].advcfg & STM32_GPIO_ADVCFGR_DLYPATH_MASK;
+
+ ret = stm32_pconf_set_skew_delay(bank, offset,
+ bank->pin_backup[offset].skew_delay,
+ is_input);
+ if (ret)
+ return ret;
+
+ ret = stm32_pconf_set_advcfgr(bank, offset, STM32_GPIO_ADVCFGR_IO_SYNC_MASK,
+ bank->pin_backup[offset].advcfg);
+ if (ret)
+ return ret;
+ }
+
if (pin_is_irq)
regmap_field_write(pctl->irqmux[offset], bank->bank_ioport_nr);
projects / thirdparty / kernel / stable.git / commitdiff
