return FALSE;
}
- if ((r_type == R_386_GOT32 || r_type == R_386_GOT32X)
+ if (r_type == R_386_GOT32X
&& (h == NULL || h->type != STT_GNU_IFUNC))
sec->need_convert_load = 1;
}
unsigned int nop;
bfd_vma nop_offset;
- if (r_type != R_386_GOT32 && r_type != R_386_GOT32X)
+ /* Don't convert R_386_GOT32 since we can't tell if it is applied
+ to "mov $foo@GOT, %reg" which isn't a load via GOT. */
+ if (r_type != R_386_GOT32X)
continue;
roff = irel->r_offset;
if (roff < 2)
continue;
- /* Addend for R_386_GOT32 and R_386_GOT32X relocations must be 0. */
+ /* Addend for R_386_GOT32X relocation must be 0. */
addend = bfd_get_32 (abfd, contents + roff);
if (addend != 0)
continue;
modrm = bfd_get_8 (abfd, contents + roff - 1);
baseless = (modrm & 0xc7) == 0x5;
- if (r_type == R_386_GOT32X
- && baseless
+ if (baseless
&& bfd_link_pic (link_info))
{
/* For PIC, disallow R_386_GOT32X without a base register
- since we don't know what the GOT base is. Allow
- R_386_GOT32 for existing object files. */
+ since we don't know what the GOT base is. */
const char *name;
if (r_symndx < symtab_hdr->sh_info)
/* It is OK to convert mov to lea. */
if (opcode != 0x8b)
{
- /* Only convert R_386_GOT32X relocation for call, jmp or
- one of adc, add, and, cmp, or, sbb, sub, test, xor
- instructions. */
- if (r_type != R_386_GOT32X)
- continue;
-
/* It is OK to convert indirect branch to direct branch. It
is OK to convert adc, add, and, cmp, or, sbb, sub, test,
xor only when PIC is false. */
continue;
}
- /* Try to convert R_386_GOT32 and R_386_GOT32X. Get the symbol
- referred to by the reloc. */
+ /* Try to convert R_386_GOT32X. Get the symbol referred to by
+ the reloc. */
if (r_symndx < symtab_hdr->sh_info)
{
isym = bfd_sym_from_r_symndx (&htab->sym_cache,
{
/* Convert "mov foo@GOT(%reg1), %reg2" to
"lea foo@GOTOFF(%reg1), %reg2". */
- if (r_type == R_386_GOT32X
- && (baseless || !bfd_link_pic (link_info)))
+ if (baseless || !bfd_link_pic (link_info))
{
r_type = R_386_32;
/* For R_386_32, convert