]> git.ipfire.org Git - thirdparty/kernel/stable.git/commitdiff
scsi: ufs: ufs-qcom: Disable lane clocks during phy hibern8
authorPalash Kambar <quic_pkambar@quicinc.com>
Tue, 9 Sep 2025 05:51:49 +0000 (11:21 +0530)
committerMartin K. Petersen <martin.petersen@oracle.com>
Tue, 16 Sep 2025 01:50:41 +0000 (21:50 -0400)
Currently, the UFS lane clocks remain enabled even after the link enters
the Hibern8 state and are only disabled during runtime/system
suspend.This patch modifies the behavior to disable the lane clocks
during ufs_qcom_setup_clocks(), which is invoked shortly after the link
enters Hibern8 via gate work.

While hibern8_notify() offers immediate control, toggling clocks on
every transition isn't ideal due to varied contexts like clock scaling.
Since setup_clocks() manages PHY/controller resources and is invoked
soon after Hibern8 entry, it serves as a central and stable point for
clock gating.

Signed-off-by: Palash Kambar <quic_pkambar@quicinc.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
Message-ID: <20250909055149.2068737-1-quic_pkambar@quicinc.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
drivers/ufs/host/ufs-qcom.c

index da6a88d875a12d20ed6d128a2943cd7a6f639be8..0c792fec76150ca7e39a0b431eb83eed247dfbbe 100644 (file)
@@ -1183,6 +1183,13 @@ static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on,
        case PRE_CHANGE:
                if (on) {
                        ufs_qcom_icc_update_bw(host);
+                       if (ufs_qcom_is_link_hibern8(hba)) {
+                               err = ufs_qcom_enable_lane_clks(host);
+                               if (err) {
+                                       dev_err(hba->dev, "enable lane clks failed, ret=%d\n", err);
+                                       return err;
+                               }
+                       }
                } else {
                        if (!ufs_qcom_is_link_active(hba)) {
                                /* disable device ref_clk */
@@ -1208,6 +1215,9 @@ static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on,
                        if (ufshcd_is_hs_mode(&hba->pwr_info))
                                ufs_qcom_dev_ref_clk_ctrl(host, true);
                } else {
+                       if (ufs_qcom_is_link_hibern8(hba))
+                               ufs_qcom_disable_lane_clks(host);
+
                        ufs_qcom_icc_set_bw(host, ufs_qcom_bw_table[MODE_MIN][0][0].mem_bw,
                                            ufs_qcom_bw_table[MODE_MIN][0][0].cfg_bw);
                }