]> git.ipfire.org Git - thirdparty/kernel/stable.git/commitdiff
pinctrl: stm32: consider the GPIO offset to expose all the GPIO lines
authorFabien Dessenne <fabien.dessenne@foss.st.com>
Wed, 15 Dec 2021 09:58:08 +0000 (10:58 +0100)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Wed, 29 Dec 2021 11:28:55 +0000 (12:28 +0100)
commit b67210cc217f9ca1c576909454d846970c13dfd4 upstream.

Consider the GPIO controller offset (from "gpio-ranges") to compute the
maximum GPIO line number.
This fixes an issue where gpio-ranges uses a non-null offset.
  e.g.: gpio-ranges = <&pinctrl 6 86 10>
        In that case the last valid GPIO line is not 9 but 15 (6 + 10 - 1)

Cc: stable@vger.kernel.org
Fixes: 67e2996f72c7 ("pinctrl: stm32: fix the reported number of GPIO lines per bank")
Reported-by: Christoph Fritz <chf.fritz@googlemail.com>
Signed-off-by: Fabien Dessenne <fabien.dessenne@foss.st.com>
Link: https://lore.kernel.org/r/20211215095808.621716-1-fabien.dessenne@foss.st.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
drivers/pinctrl/stm32/pinctrl-stm32.c

index dfd8888a222a46068068a100cf709d985b22f901..8934b4878fa8542086d300e7d9003af2d4b2f1ce 100644 (file)
@@ -1251,10 +1251,10 @@ static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl,
                bank_nr = args.args[1] / STM32_GPIO_PINS_PER_BANK;
                bank->gpio_chip.base = args.args[1];
 
-               npins = args.args[2];
-               while (!of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3,
-                                                        ++i, &args))
-                       npins += args.args[2];
+               /* get the last defined gpio line (offset + nb of pins) */
+               npins = args.args[0] + args.args[2];
+               while (!of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, ++i, &args))
+                       npins = max(npins, (int)(args.args[0] + args.args[2]));
        } else {
                bank_nr = pctl->nbanks;
                bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK;