arm: [MVE intrinsics] factorize vmlaldavq vmlaldavxq vmlsldavq vmlsldavxq

Factorize vmlaldavq, vmlaldavxq, vmlsldavq, vmlsldavxq builtins so
that they use parameterized names.

2022-10-25  Christophe Lyon  <christophe.lyon@arm.com>

	gcc/
	* config/arm/iterators.md (MVE_VMLxLDAVxQ, MVE_VMLxLDAVxQ_P): New.
	(mve_insn): Add vmlaldav, vmlaldavx, vmlsldav, vmlsldavx.
	(supf): Add VMLALDAVXQ_S, VMLSLDAVQ_S, VMLSLDAVXQ_S,
	VMLALDAVXQ_P_S, VMLSLDAVQ_P_S, VMLSLDAVXQ_P_S.
	* config/arm/mve.md (mve_vmlaldavq_<supf><mode>)
	(mve_vmlaldavxq_s<mode>, mve_vmlsldavq_s<mode>)
	(mve_vmlsldavxq_s<mode>): Merge into ...
	(@mve_<mve_insn>q_<supf><mode>): ... this.
	(mve_vmlaldavq_p_<supf><mode>, mve_vmlaldavxq_p_s<mode>)
	(mve_vmlsldavq_p_s<mode>, mve_vmlsldavxq_p_s<mode>): Merge into
	...
	(@mve_<mve_insn>q_p_<supf><mode>): ... this.

diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index cafb62a574e33764c5ca8dd4e39820247260db53..227ba52aed5fbfac7b8f9887a8d6e9e8a1b9abc3 100644 (file)
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -727,6 +727,20 @@
                     VMLADAVAXQ_P_S
                     ])
 
+(define_int_iterator MVE_VMLxLDAVxQ [
+                    VMLALDAVQ_S VMLALDAVQ_U
+                    VMLALDAVXQ_S
+                    VMLSLDAVQ_S
+                    VMLSLDAVXQ_S
+                    ])
+
+(define_int_iterator MVE_VMLxLDAVxQ_P [
+                    VMLALDAVQ_P_S VMLALDAVQ_P_U
+                    VMLALDAVXQ_P_S
+                    VMLSLDAVQ_P_S
+                    VMLSLDAVXQ_P_S
+                    ])
+
 (define_int_iterator MVE_MOVN [
                     VMOVNBQ_S VMOVNBQ_U
                     VMOVNTQ_S VMOVNTQ_U
@@ -855,6 +869,10 @@
                 (VMLADAVQ_S "vmladav") (VMLADAVQ_U "vmladav")
                 (VMLADAVXQ_P_S "vmladavx")
                 (VMLADAVXQ_S "vmladavx")
+                (VMLALDAVQ_P_S "vmlaldav") (VMLALDAVQ_P_U "vmlaldav")
+                (VMLALDAVQ_S "vmlaldav") (VMLALDAVQ_U "vmlaldav")
+                (VMLALDAVXQ_P_S "vmlaldavx")
+                (VMLALDAVXQ_S "vmlaldavx")
                 (VMLAQ_M_N_S "vmla") (VMLAQ_M_N_U "vmla")
                 (VMLASQ_M_N_S "vmlas") (VMLASQ_M_N_U "vmlas")
                 (VMLSDAVAQ_P_S "vmlsdava")
@@ -865,6 +883,10 @@
                 (VMLSDAVQ_S "vmlsdav")
                 (VMLSDAVXQ_P_S "vmlsdavx")
                 (VMLSDAVXQ_S "vmlsdavx")
+                (VMLSLDAVQ_P_S "vmlsldav")
+                (VMLSLDAVQ_S "vmlsldav")
+                (VMLSLDAVXQ_P_S "vmlsldavx")
+                (VMLSLDAVXQ_S "vmlsldavx")
                 (VMOVLBQ_M_S "vmovlb") (VMOVLBQ_M_U "vmovlb")
                 (VMOVLBQ_S "vmovlb") (VMOVLBQ_U "vmovlb")
                 (VMOVLTQ_M_S "vmovlt") (VMOVLTQ_M_U "vmovlt")
@@ -2295,6 +2317,12 @@
                       (VMLSDAVQ_S "s")
                       (VMLSDAVXQ_P_S "s")
                       (VMLSDAVXQ_S "s")
+                      (VMLALDAVXQ_S "s")
+                      (VMLSLDAVQ_S "s")
+                      (VMLSLDAVXQ_S "s")
+                      (VMLALDAVXQ_P_S "s")
+                      (VMLSLDAVQ_P_S "s")
+                      (VMLSLDAVXQ_P_S "s")
                       ])
 
 ;; Both kinds of return insn.

diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index df7829bc18332d2a7c7ac606aaaf26c13366d2b0..584e6129ea516776e37685098adb64052826b5f9 100644 (file)
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -1405,62 +1405,20 @@
 ])
 
 ;;
-;; [vmlaldavq_u, vmlaldavq_s])
+;; [vmlaldavq_u, vmlaldavq_s]
+;; [vmlaldavxq_s]
+;; [vmlsldavq_s]
+;; [vmlsldavxq_s]
 ;;
-(define_insn "mve_vmlaldavq_<supf><mode>"
-  [
-   (set (match_operand:DI 0 "s_register_operand" "=r")
-       (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w")
-                   (match_operand:MVE_5 2 "s_register_operand" "w")]
-        VMLALDAVQ))
-  ]
-  "TARGET_HAVE_MVE"
-  "vmlaldav.<supf>%#<V_sz_elem>        %Q0, %R0, %q1, %q2"
-  [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vmlaldavxq_s])
-;;
-(define_insn "mve_vmlaldavxq_s<mode>"
-  [
-   (set (match_operand:DI 0 "s_register_operand" "=r")
-       (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w")
-                   (match_operand:MVE_5 2 "s_register_operand" "w")]
-        VMLALDAVXQ_S))
-  ]
-  "TARGET_HAVE_MVE"
-  "vmlaldavx.s%#<V_sz_elem> %Q0, %R0, %q1, %q2"
-  [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vmlsldavq_s])
-;;
-(define_insn "mve_vmlsldavq_s<mode>"
-  [
-   (set (match_operand:DI 0 "s_register_operand" "=r")
-       (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w")
-                   (match_operand:MVE_5 2 "s_register_operand" "w")]
-        VMLSLDAVQ_S))
-  ]
-  "TARGET_HAVE_MVE"
-  "vmlsldav.s%#<V_sz_elem> %Q0, %R0, %q1, %q2"
-  [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vmlsldavxq_s])
-;;
-(define_insn "mve_vmlsldavxq_s<mode>"
+(define_insn "@mve_<mve_insn>q_<supf><mode>"
   [
    (set (match_operand:DI 0 "s_register_operand" "=r")
        (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w")
                    (match_operand:MVE_5 2 "s_register_operand" "w")]
-        VMLSLDAVXQ_S))
+        MVE_VMLxLDAVxQ))
   ]
   "TARGET_HAVE_MVE"
-  "vmlsldavx.s%#<V_sz_elem> %Q0, %R0, %q1, %q2"
+  "<mve_insn>.<supf>%#<V_sz_elem>\t%Q0, %R0, %q1, %q2"
   [(set_attr "type" "mve_move")
 ])
 
@@ -2666,37 +2624,25 @@
 ])
 
 ;;
-;; [vmlaldavq_p_u, vmlaldavq_p_s])
+;; [vmlaldavq_p_u, vmlaldavq_p_s]
+;; [vmlaldavxq_p_s]
+;; [vmlsldavq_p_s]
+;; [vmlsldavxq_p_s]
 ;;
-(define_insn "mve_vmlaldavq_p_<supf><mode>"
+(define_insn "@mve_<mve_insn>q_p_<supf><mode>"
   [
    (set (match_operand:DI 0 "s_register_operand" "=r")
        (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w")
                       (match_operand:MVE_5 2 "s_register_operand" "w")
                       (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
-        VMLALDAVQ_P))
+        MVE_VMLxLDAVxQ_P))
   ]
   "TARGET_HAVE_MVE"
-  "vpst\;vmlaldavt.<supf>%#<V_sz_elem> %Q0, %R0, %q1, %q2"
+  "vpst\;<mve_insn>t.<supf>%#<V_sz_elem>\t%Q0, %R0, %q1, %q2"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
 ;;
-;; [vmlaldavxq_p_s])
-;;
-(define_insn "mve_vmlaldavxq_p_s<mode>"
-  [
-   (set (match_operand:DI 0 "s_register_operand" "=r")
-       (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w")
-                      (match_operand:MVE_5 2 "s_register_operand" "w")
-                      (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
-        VMLALDAVXQ_P_S))
-  ]
-  "TARGET_HAVE_MVE"
-  "vpst\;vmlaldavxt.s%#<V_sz_elem>\t%Q0, %R0, %q1, %q2"
-  [(set_attr "type" "mve_move")
-   (set_attr "length""8")])
-;;
 ;; [vmlsldavaq_s])
 ;;
 (define_insn "mve_vmlsldavaq_s<mode>"
@@ -2728,38 +2674,6 @@
   [(set_attr "type" "mve_move")
 ])
 
-;;
-;; [vmlsldavq_p_s])
-;;
-(define_insn "mve_vmlsldavq_p_s<mode>"
-  [
-   (set (match_operand:DI 0 "s_register_operand" "=r")
-       (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w")
-                      (match_operand:MVE_5 2 "s_register_operand" "w")
-                      (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
-        VMLSLDAVQ_P_S))
-  ]
-  "TARGET_HAVE_MVE"
-  "vpst\;vmlsldavt.s%#<V_sz_elem> %Q0, %R0, %q1, %q2"
-  [(set_attr "type" "mve_move")
-   (set_attr "length""8")])
-
-;;
-;; [vmlsldavxq_p_s])
-;;
-(define_insn "mve_vmlsldavxq_p_s<mode>"
-  [
-   (set (match_operand:DI 0 "s_register_operand" "=r")
-       (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w")
-                      (match_operand:MVE_5 2 "s_register_operand" "w")
-                      (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
-        VMLSLDAVXQ_P_S))
-  ]
-  "TARGET_HAVE_MVE"
-  "vpst\;vmlsldavxt.s%#<V_sz_elem> %Q0, %R0, %q1, %q2"
-  [(set_attr "type" "mve_move")
-   (set_attr "length""8")])
-
 ;;
 ;; [vmovlbq_m_u, vmovlbq_m_s])
 ;; [vmovltq_m_u, vmovltq_m_s])