]> git.ipfire.org Git - thirdparty/linux.git/commitdiff
drm/amdgpu: Use the right function for hdp flush
authorLijo Lazar <lijo.lazar@amd.com>
Fri, 11 Apr 2025 12:10:26 +0000 (17:40 +0530)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 16 Apr 2025 19:57:46 +0000 (15:57 -0400)
There are a few prechecks made before HDP flush like a flush is not
required on APU bare metal. Using hdp callback directly bypasses those
checks. Use amdgpu_device_flush_hdp which takes care of prechecks.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit 1d9bff4cf8c53d33ee2ff1b11574e5da739ce61c)

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
drivers/gpu/drm/amd/amdgpu/psp_v14_0.c

index a63ce747863f10d9586cf058a7d114d888ea3808..23e6a05359c24b682ed05f2812585892a1669f31 100644 (file)
@@ -6114,7 +6114,7 @@ static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
        }
 
        if (amdgpu_emu_mode == 1)
-               adev->hdp.funcs->flush_hdp(adev, NULL);
+               amdgpu_device_flush_hdp(adev, NULL);
 
        tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL);
        tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
@@ -6192,7 +6192,7 @@ static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev)
        }
 
        if (amdgpu_emu_mode == 1)
-               adev->hdp.funcs->flush_hdp(adev, NULL);
+               amdgpu_device_flush_hdp(adev, NULL);
 
        tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL);
        tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0);
@@ -6269,7 +6269,7 @@ static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)
        }
 
        if (amdgpu_emu_mode == 1)
-               adev->hdp.funcs->flush_hdp(adev, NULL);
+               amdgpu_device_flush_hdp(adev, NULL);
 
        tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL);
        tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
@@ -6644,7 +6644,7 @@ static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev)
        }
 
        if (amdgpu_emu_mode == 1)
-               adev->hdp.funcs->flush_hdp(adev, NULL);
+               amdgpu_device_flush_hdp(adev, NULL);
 
        tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL);
        tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
index d57db42f9536008494874fbf510d607ed6321a74..2a5c2a1ae3c74f36cbc9575c76331ade3bd99b85 100644 (file)
@@ -2428,7 +2428,7 @@ static int gfx_v11_0_config_me_cache(struct amdgpu_device *adev, uint64_t addr)
        }
 
        if (amdgpu_emu_mode == 1)
-               adev->hdp.funcs->flush_hdp(adev, NULL);
+               amdgpu_device_flush_hdp(adev, NULL);
 
        tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL);
        tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
@@ -2472,7 +2472,7 @@ static int gfx_v11_0_config_pfp_cache(struct amdgpu_device *adev, uint64_t addr)
        }
 
        if (amdgpu_emu_mode == 1)
-               adev->hdp.funcs->flush_hdp(adev, NULL);
+               amdgpu_device_flush_hdp(adev, NULL);
 
        tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL);
        tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
@@ -2517,7 +2517,7 @@ static int gfx_v11_0_config_mec_cache(struct amdgpu_device *adev, uint64_t addr)
        }
 
        if (amdgpu_emu_mode == 1)
-               adev->hdp.funcs->flush_hdp(adev, NULL);
+               amdgpu_device_flush_hdp(adev, NULL);
 
        tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL);
        tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
@@ -3153,7 +3153,7 @@ static int gfx_v11_0_cp_gfx_load_pfp_microcode_rs64(struct amdgpu_device *adev)
        amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_data_obj);
 
        if (amdgpu_emu_mode == 1)
-               adev->hdp.funcs->flush_hdp(adev, NULL);
+               amdgpu_device_flush_hdp(adev, NULL);
 
        WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO,
                lower_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
@@ -3371,7 +3371,7 @@ static int gfx_v11_0_cp_gfx_load_me_microcode_rs64(struct amdgpu_device *adev)
        amdgpu_bo_unreserve(adev->gfx.me.me_fw_data_obj);
 
        if (amdgpu_emu_mode == 1)
-               adev->hdp.funcs->flush_hdp(adev, NULL);
+               amdgpu_device_flush_hdp(adev, NULL);
 
        WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO,
                lower_32_bits(adev->gfx.me.me_fw_gpu_addr));
@@ -4541,7 +4541,7 @@ static int gfx_v11_0_gfxhub_enable(struct amdgpu_device *adev)
        if (r)
                return r;
 
-       adev->hdp.funcs->flush_hdp(adev, NULL);
+       amdgpu_device_flush_hdp(adev, NULL);
 
        value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ?
                false : true;
index e7b58e470292717279b9d72e60744e4d5bab95d7..62a257a4a3e9b5b34dcd7a7f8cfc318de310a306 100644 (file)
@@ -2324,7 +2324,7 @@ static int gfx_v12_0_cp_gfx_load_pfp_microcode_rs64(struct amdgpu_device *adev)
        amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_data_obj);
 
        if (amdgpu_emu_mode == 1)
-               adev->hdp.funcs->flush_hdp(adev, NULL);
+               amdgpu_device_flush_hdp(adev, NULL);
 
        WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO,
                lower_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
@@ -2468,7 +2468,7 @@ static int gfx_v12_0_cp_gfx_load_me_microcode_rs64(struct amdgpu_device *adev)
        amdgpu_bo_unreserve(adev->gfx.me.me_fw_data_obj);
 
        if (amdgpu_emu_mode == 1)
-               adev->hdp.funcs->flush_hdp(adev, NULL);
+               amdgpu_device_flush_hdp(adev, NULL);
 
        WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO,
                lower_32_bits(adev->gfx.me.me_fw_gpu_addr));
@@ -3426,7 +3426,7 @@ static int gfx_v12_0_gfxhub_enable(struct amdgpu_device *adev)
        if (r)
                return r;
 
-       adev->hdp.funcs->flush_hdp(adev, NULL);
+       amdgpu_device_flush_hdp(adev, NULL);
 
        value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ?
                false : true;
index 95d894a231fcfc43e7dee140f739d26aafc80e75..809b3a882d0d72be5ac24a4a372348f0b401e5ff 100644 (file)
@@ -268,7 +268,7 @@ static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
        ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng;
 
        /* flush hdp cache */
-       adev->hdp.funcs->flush_hdp(adev, NULL);
+       amdgpu_device_flush_hdp(adev, NULL);
 
        /* This is necessary for SRIOV as well as for GFXOFF to function
         * properly under bare metal
@@ -969,7 +969,7 @@ static int gmc_v10_0_gart_enable(struct amdgpu_device *adev)
        adev->hdp.funcs->init_registers(adev);
 
        /* Flush HDP after it is initialized */
-       adev->hdp.funcs->flush_hdp(adev, NULL);
+       amdgpu_device_flush_hdp(adev, NULL);
 
        value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ?
                false : true;
index ad099f136f84ebfd17901df5c4c2673ce691cc22..e74e26b6a4f23c053261374dbc6fdb30f0b62720 100644 (file)
@@ -229,7 +229,7 @@ static void gmc_v11_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
        ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng;
 
        /* flush hdp cache */
-       adev->hdp.funcs->flush_hdp(adev, NULL);
+       amdgpu_device_flush_hdp(adev, NULL);
 
        /* This is necessary for SRIOV as well as for GFXOFF to function
         * properly under bare metal
@@ -899,7 +899,7 @@ static int gmc_v11_0_gart_enable(struct amdgpu_device *adev)
                return r;
 
        /* Flush HDP after it is initialized */
-       adev->hdp.funcs->flush_hdp(adev, NULL);
+       amdgpu_device_flush_hdp(adev, NULL);
 
        value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ?
                false : true;
index 05c026d0b0d96ae3b275578791df40ce2dbd88ae..c6f290704d4731eb50bce8b30684f42ecf942c0e 100644 (file)
@@ -297,7 +297,7 @@ static void gmc_v12_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
                return;
 
        /* flush hdp cache */
-       adev->hdp.funcs->flush_hdp(adev, NULL);
+       amdgpu_device_flush_hdp(adev, NULL);
 
        /* This is necessary for SRIOV as well as for GFXOFF to function
         * properly under bare metal
@@ -881,7 +881,7 @@ static int gmc_v12_0_gart_enable(struct amdgpu_device *adev)
                return r;
 
        /* Flush HDP after it is initialized */
-       adev->hdp.funcs->flush_hdp(adev, NULL);
+       amdgpu_device_flush_hdp(adev, NULL);
 
        value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ?
                false : true;
index 783e0c3b86b4c4a56fbbfa2cf7ca1a66df61a1de..5effe8327d29fbf1aa2388affbb08e506db066c1 100644 (file)
@@ -2435,7 +2435,7 @@ static int gmc_v9_0_hw_init(struct amdgpu_ip_block *ip_block)
        adev->hdp.funcs->init_registers(adev);
 
        /* After HDP is initialized, flush HDP.*/
-       adev->hdp.funcs->flush_hdp(adev, NULL);
+       amdgpu_device_flush_hdp(adev, NULL);
 
        if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
                value = false;
index bb5dfc410a667fc226154968b5134b395e51792d..215543575f477c9a981e18f8bc0f40b2ed827572 100644 (file)
@@ -533,7 +533,7 @@ static int psp_v11_0_memory_training(struct psp_context *psp, uint32_t ops)
                        }
 
                        memcpy_toio(adev->mman.aper_base_kaddr, buf, sz);
-                       adev->hdp.funcs->flush_hdp(adev, NULL);
+                       amdgpu_device_flush_hdp(adev, NULL);
                        vfree(buf);
                        drm_dev_exit(idx);
                } else {
index cc621064610f1d5d0b3b433248fd139291b485e2..afdf8ce3b4c59e7778688cfaae55a64285aebf44 100644 (file)
@@ -610,7 +610,7 @@ static int psp_v13_0_memory_training(struct psp_context *psp, uint32_t ops)
                        }
 
                        memcpy_toio(adev->mman.aper_base_kaddr, buf, sz);
-                       adev->hdp.funcs->flush_hdp(adev, NULL);
+                       amdgpu_device_flush_hdp(adev, NULL);
                        vfree(buf);
                        drm_dev_exit(idx);
                } else {
index 7c49c3f3c3881ee0cddc934e6fe57f0eef01e443..256288c6cd78ef968130f368676adea484532776 100644 (file)
@@ -498,7 +498,7 @@ static int psp_v14_0_memory_training(struct psp_context *psp, uint32_t ops)
                        }
 
                        memcpy_toio(adev->mman.aper_base_kaddr, buf, sz);
-                       adev->hdp.funcs->flush_hdp(adev, NULL);
+                       amdgpu_device_flush_hdp(adev, NULL);
                        vfree(buf);
                        drm_dev_exit(idx);
                } else {