arm64: dts: ti: k3-j784s4-evm: Enable Main CPSW2G node and add aliases for it

Enable MAIN CPSW2G and add alias for it to enable Linux to fetch
MAC Address for the port directly from U-Boot.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Signed-off-by: Chintan Vankar <c-vankar@ti.com>
Link: https://lore.kernel.org/r/20240502091002.3659435-4-c-vankar@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
index 2fe6a582ceab2b0573d42a2d8d9a397c800228a1..bc5c22383105c02526ace076cb8130af04654e00 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
@@ -28,6 +28,7 @@
                i2c0 = &wkup_i2c0;
                i2c3 = &main_i2c0;
                ethernet0 = &mcu_cpsw_port1;
+               ethernet1 = &main_cpsw1_port1;
        };
 
        memory@80000000 {
@@ -281,6 +282,30 @@
 
 &main_pmx0 {
        bootph-all;
+       main_cpsw2g_default_pins: main-cpsw2g-default-pins {
+               pinctrl-single,pins = <
+                       J784S4_IOPAD(0x0b8, PIN_INPUT, 6) /* (AC34) MCASP1_ACLKX.RGMII1_RD0 */
+                       J784S4_IOPAD(0x0a0, PIN_INPUT, 6) /* (AD34) MCASP0_AXR12.RGMII1_RD1 */
+                       J784S4_IOPAD(0x0a4, PIN_INPUT, 6) /* (AJ36) MCASP0_AXR13.RGMII1_RD2 */
+                       J784S4_IOPAD(0x0a8, PIN_INPUT, 6) /* (AF34) MCASP0_AXR14.RGMII1_RD3 */
+                       J784S4_IOPAD(0x0b0, PIN_INPUT, 6) /* (AL33) MCASP1_AXR3.RGMII1_RXC */
+                       J784S4_IOPAD(0x0ac, PIN_INPUT, 6) /* (AE34) MCASP0_AXR15.RGMII1_RX_CTL */
+                       J784S4_IOPAD(0x08c, PIN_INPUT, 6) /* (AE35) MCASP0_AXR7.RGMII1_TD0 */
+                       J784S4_IOPAD(0x090, PIN_INPUT, 6) /* (AC35) MCASP0_AXR8.RGMII1_TD1 */
+                       J784S4_IOPAD(0x094, PIN_INPUT, 6) /* (AG35) MCASP0_AXR9.RGMII1_TD2 */
+                       J784S4_IOPAD(0x098, PIN_INPUT, 6) /* (AH36) MCASP0_AXR10.RGMII1_TD3 */
+                       J784S4_IOPAD(0x0b4, PIN_INPUT, 6) /* (AL34) MCASP1_AXR4.RGMII1_TXC */
+                       J784S4_IOPAD(0x09c, PIN_INPUT, 6) /* (AF35) MCASP0_AXR11.RGMII1_TX_CTL */
+               >;
+       };
+
+       main_cpsw2g_mdio_default_pins: main-cpsw2g-mdio-default-pins {
+               pinctrl-single,pins = <
+                       J784S4_IOPAD(0x0c0, PIN_INPUT, 6) /* (AD38) MCASP1_AXR0.MDIO0_MDC */
+                       J784S4_IOPAD(0x0bc, PIN_INPUT, 6) /* (AD33) MCASP1_AFSX.MDIO0_MDIO */
+               >;
+       };
+
        main_uart8_pins_default: main-uart8-default-pins {
                bootph-all;
                pinctrl-single,pins = <
@@ -833,6 +858,31 @@
        phy-handle = <&mcu_phy0>;
 };
 
+&main_cpsw1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&main_cpsw2g_default_pins>;
+       status = "okay";
+};
+
+&main_cpsw1_mdio {
+       pinctrl-names = "default";
+       pinctrl-0 = <&main_cpsw2g_mdio_default_pins>;
+       status = "okay";
+
+       main_cpsw1_phy0: ethernet-phy@0 {
+               reg = <0>;
+               ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+               ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+               ti,min-output-impedance;
+       };
+};
+
+&main_cpsw1_port1 {
+       phy-mode = "rgmii-rxid";
+       phy-handle = <&main_cpsw1_phy0>;
+       status = "okay";
+};
+
 &mailbox0_cluster0 {
        status = "okay";
        interrupts = <436>;