--- /dev/null
+From 1ff60ddb84bb9ff6fa182710c4e08b66badf918c Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 30 Aug 2013 16:18:35 -0400
+Subject: drm/radeon/dpm: make sure dc performance level limits are valid (BTC-SI) (v2)
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit 1ff60ddb84bb9ff6fa182710c4e08b66badf918c upstream.
+
+Check to make sure the dc limits are valid before using them.
+Some systems may not have a dc limits table. In that case just
+use the ac limits. This fixes hangs on systems when the power
+state is changed when on battery (dc) due to invalid performance
+state parameters.
+
+Should fix:
+https://bugs.freedesktop.org/show_bug.cgi?id=68708
+
+v2: fix up limits in dpm_init()
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/btc_dpm.c | 6 ++++++
+ drivers/gpu/drm/radeon/ni_dpm.c | 6 ++++++
+ drivers/gpu/drm/radeon/si_dpm.c | 6 ++++++
+ 3 files changed, 18 insertions(+)
+
+--- a/drivers/gpu/drm/radeon/btc_dpm.c
++++ b/drivers/gpu/drm/radeon/btc_dpm.c
+@@ -2699,6 +2699,12 @@ int btc_dpm_init(struct radeon_device *r
+ else
+ rdev->pm.dpm.dyn_state.sclk_mclk_delta = 10000;
+
++ /* make sure dc limits are valid */
++ if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
++ (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
++ rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
++ rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
++
+ return 0;
+ }
+
+--- a/drivers/gpu/drm/radeon/ni_dpm.c
++++ b/drivers/gpu/drm/radeon/ni_dpm.c
+@@ -4270,6 +4270,12 @@ int ni_dpm_init(struct radeon_device *rd
+
+ ni_pi->use_power_boost_limit = true;
+
++ /* make sure dc limits are valid */
++ if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
++ (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
++ rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
++ rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
++
+ return 0;
+ }
+
+--- a/drivers/gpu/drm/radeon/si_dpm.c
++++ b/drivers/gpu/drm/radeon/si_dpm.c
+@@ -6401,6 +6401,12 @@ int si_dpm_init(struct radeon_device *rd
+
+ si_initialize_powertune_defaults(rdev);
+
++ /* make sure dc limits are valid */
++ if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
++ (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
++ rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
++ rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
++
+ return 0;
+ }
+
--- /dev/null
+From fb93df1c2d8b3b1fb16d6ee9e32554e0c038815d Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Tue, 27 Aug 2013 12:36:01 -0400
+Subject: drm/radeon: fix handling of variable sized arrays for router objects
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit fb93df1c2d8b3b1fb16d6ee9e32554e0c038815d upstream.
+
+The table has the following format:
+
+typedef struct _ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT //usSrcDstTableOffset pointing to this structure
+{
+ UCHAR ucNumberOfSrc;
+ USHORT usSrcObjectID[1];
+ UCHAR ucNumberOfDst;
+ USHORT usDstObjectID[1];
+}ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT;
+
+usSrcObjectID[] and usDstObjectID[] are variably sized, so we
+can't access them directly. Use pointers and update the offset
+appropriately when accessing the Dst members.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/radeon_atombios.c | 9 ++++++---
+ 1 file changed, 6 insertions(+), 3 deletions(-)
+
+--- a/drivers/gpu/drm/radeon/radeon_atombios.c
++++ b/drivers/gpu/drm/radeon/radeon_atombios.c
+@@ -711,13 +711,16 @@ bool radeon_get_atom_connector_info_from
+ (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
+ (ctx->bios + data_offset +
+ le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
++ u8 *num_dst_objs = (u8 *)
++ ((u8 *)router_src_dst_table + 1 +
++ (router_src_dst_table->ucNumberOfSrc * 2));
++ u16 *dst_objs = (u16 *)(num_dst_objs + 1);
+ int enum_id;
+
+ router.router_id = router_obj_id;
+- for (enum_id = 0; enum_id < router_src_dst_table->ucNumberOfDst;
+- enum_id++) {
++ for (enum_id = 0; enum_id < (*num_dst_objs); enum_id++) {
+ if (le16_to_cpu(path->usConnObjectId) ==
+- le16_to_cpu(router_src_dst_table->usDstObjectID[enum_id]))
++ le16_to_cpu(dst_objs[enum_id]))
+ break;
+ }
+
--- /dev/null
+From acf88deb8ddbb73acd1c3fa32fde51af9153227f Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Mon, 26 Aug 2013 17:52:12 -0400
+Subject: drm/radeon: fix resume on some rs4xx boards (v2)
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit acf88deb8ddbb73acd1c3fa32fde51af9153227f upstream.
+
+Setting MC_MISC_CNTL.GART_INDEX_REG_EN causes hangs on
+some boards on resume. The systems seem to work fine
+without touching this bit so leave it as is.
+
+v2: read-modify-write the GART_INDEX_REG_EN bit.
+I suspect the problem is that we are losing the other
+settings in the register.
+
+fixes:
+https://bugs.freedesktop.org/show_bug.cgi?id=52952
+
+Reported-by: Ondrej Zary <linux@rainbow-software.org>
+Tested-by: Daniel Tobias <dan.g.tob@gmail.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/rs400.c | 9 ++++++---
+ 1 file changed, 6 insertions(+), 3 deletions(-)
+
+--- a/drivers/gpu/drm/radeon/rs400.c
++++ b/drivers/gpu/drm/radeon/rs400.c
+@@ -174,10 +174,13 @@ int rs400_gart_enable(struct radeon_devi
+ /* FIXME: according to doc we should set HIDE_MMCFG_BAR=0,
+ * AGPMODE30=0 & AGP30ENHANCED=0 in NB_CNTL */
+ if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) {
+- WREG32_MC(RS480_MC_MISC_CNTL,
+- (RS480_GART_INDEX_REG_EN | RS690_BLOCK_GFX_D3_EN));
++ tmp = RREG32_MC(RS480_MC_MISC_CNTL);
++ tmp |= RS480_GART_INDEX_REG_EN | RS690_BLOCK_GFX_D3_EN;
++ WREG32_MC(RS480_MC_MISC_CNTL, tmp);
+ } else {
+- WREG32_MC(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
++ tmp = RREG32_MC(RS480_MC_MISC_CNTL);
++ tmp |= RS480_GART_INDEX_REG_EN;
++ WREG32_MC(RS480_MC_MISC_CNTL, tmp);
+ }
+ /* Enable gart */
+ WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | size_reg));
--- /dev/null
+From e5b9e7503eb1f4884efa3b321d3cc47806779202 Mon Sep 17 00:00:00 2001
+From: Tom Stellard <thomas.stellard@amd.com>
+Date: Fri, 16 Aug 2013 17:47:39 -0400
+Subject: drm/radeon/si: Add support for CP DMA to CS checker for compute v2
+
+From: Tom Stellard <thomas.stellard@amd.com>
+
+commit e5b9e7503eb1f4884efa3b321d3cc47806779202 upstream.
+
+Also add a new RADEON_INFO query to check that CP DMA packets are
+supported on the compute ring.
+
+CP DMA has been supported since the 3.8 kernel, but due to an oversight
+we forgot to teach the CS checker that the CP DMA packet was legal for
+the compute ring on Southern Islands GPUs.
+
+This patch fixes a bug where the radeon driver will incorrectly reject a legal
+CP DMA packet from user space. I would like to have the patch
+backported to stable so that we don't have to require Mesa users to use a
+bleeding edge kernel in order to take advantage of this feature which
+is already present in the stable kernels (3.8 and newer).
+
+v2:
+ - Don't bump kms version, so this patch can be backported to stable
+ kernels.
+
+Signed-off-by: Tom Stellard <thomas.stellard@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/radeon_kms.c | 3 +
+ drivers/gpu/drm/radeon/si.c | 106 ++++++++++++++++++++----------------
+ include/uapi/drm/radeon_drm.h | 2
+ 3 files changed, 66 insertions(+), 45 deletions(-)
+
+--- a/drivers/gpu/drm/radeon/radeon_kms.c
++++ b/drivers/gpu/drm/radeon/radeon_kms.c
+@@ -433,6 +433,9 @@ int radeon_info_ioctl(struct drm_device
+ return -EINVAL;
+ }
+ break;
++ case RADEON_INFO_SI_CP_DMA_COMPUTE:
++ *value = 1;
++ break;
+ default:
+ DRM_DEBUG_KMS("Invalid request %d\n", info->request);
+ return -EINVAL;
+--- a/drivers/gpu/drm/radeon/si.c
++++ b/drivers/gpu/drm/radeon/si.c
+@@ -4083,13 +4083,64 @@ static int si_vm_packet3_ce_check(struct
+ return 0;
+ }
+
++static int si_vm_packet3_cp_dma_check(u32 *ib, u32 idx)
++{
++ u32 start_reg, reg, i;
++ u32 command = ib[idx + 4];
++ u32 info = ib[idx + 1];
++ u32 idx_value = ib[idx];
++ if (command & PACKET3_CP_DMA_CMD_SAS) {
++ /* src address space is register */
++ if (((info & 0x60000000) >> 29) == 0) {
++ start_reg = idx_value << 2;
++ if (command & PACKET3_CP_DMA_CMD_SAIC) {
++ reg = start_reg;
++ if (!si_vm_reg_valid(reg)) {
++ DRM_ERROR("CP DMA Bad SRC register\n");
++ return -EINVAL;
++ }
++ } else {
++ for (i = 0; i < (command & 0x1fffff); i++) {
++ reg = start_reg + (4 * i);
++ if (!si_vm_reg_valid(reg)) {
++ DRM_ERROR("CP DMA Bad SRC register\n");
++ return -EINVAL;
++ }
++ }
++ }
++ }
++ }
++ if (command & PACKET3_CP_DMA_CMD_DAS) {
++ /* dst address space is register */
++ if (((info & 0x00300000) >> 20) == 0) {
++ start_reg = ib[idx + 2];
++ if (command & PACKET3_CP_DMA_CMD_DAIC) {
++ reg = start_reg;
++ if (!si_vm_reg_valid(reg)) {
++ DRM_ERROR("CP DMA Bad DST register\n");
++ return -EINVAL;
++ }
++ } else {
++ for (i = 0; i < (command & 0x1fffff); i++) {
++ reg = start_reg + (4 * i);
++ if (!si_vm_reg_valid(reg)) {
++ DRM_ERROR("CP DMA Bad DST register\n");
++ return -EINVAL;
++ }
++ }
++ }
++ }
++ }
++ return 0;
++}
++
+ static int si_vm_packet3_gfx_check(struct radeon_device *rdev,
+ u32 *ib, struct radeon_cs_packet *pkt)
+ {
++ int r;
+ u32 idx = pkt->idx + 1;
+ u32 idx_value = ib[idx];
+ u32 start_reg, end_reg, reg, i;
+- u32 command, info;
+
+ switch (pkt->opcode) {
+ case PACKET3_NOP:
+@@ -4190,50 +4241,9 @@ static int si_vm_packet3_gfx_check(struc
+ }
+ break;
+ case PACKET3_CP_DMA:
+- command = ib[idx + 4];
+- info = ib[idx + 1];
+- if (command & PACKET3_CP_DMA_CMD_SAS) {
+- /* src address space is register */
+- if (((info & 0x60000000) >> 29) == 0) {
+- start_reg = idx_value << 2;
+- if (command & PACKET3_CP_DMA_CMD_SAIC) {
+- reg = start_reg;
+- if (!si_vm_reg_valid(reg)) {
+- DRM_ERROR("CP DMA Bad SRC register\n");
+- return -EINVAL;
+- }
+- } else {
+- for (i = 0; i < (command & 0x1fffff); i++) {
+- reg = start_reg + (4 * i);
+- if (!si_vm_reg_valid(reg)) {
+- DRM_ERROR("CP DMA Bad SRC register\n");
+- return -EINVAL;
+- }
+- }
+- }
+- }
+- }
+- if (command & PACKET3_CP_DMA_CMD_DAS) {
+- /* dst address space is register */
+- if (((info & 0x00300000) >> 20) == 0) {
+- start_reg = ib[idx + 2];
+- if (command & PACKET3_CP_DMA_CMD_DAIC) {
+- reg = start_reg;
+- if (!si_vm_reg_valid(reg)) {
+- DRM_ERROR("CP DMA Bad DST register\n");
+- return -EINVAL;
+- }
+- } else {
+- for (i = 0; i < (command & 0x1fffff); i++) {
+- reg = start_reg + (4 * i);
+- if (!si_vm_reg_valid(reg)) {
+- DRM_ERROR("CP DMA Bad DST register\n");
+- return -EINVAL;
+- }
+- }
+- }
+- }
+- }
++ r = si_vm_packet3_cp_dma_check(ib, idx);
++ if (r)
++ return r;
+ break;
+ default:
+ DRM_ERROR("Invalid GFX packet3: 0x%x\n", pkt->opcode);
+@@ -4245,6 +4255,7 @@ static int si_vm_packet3_gfx_check(struc
+ static int si_vm_packet3_compute_check(struct radeon_device *rdev,
+ u32 *ib, struct radeon_cs_packet *pkt)
+ {
++ int r;
+ u32 idx = pkt->idx + 1;
+ u32 idx_value = ib[idx];
+ u32 start_reg, reg, i;
+@@ -4317,6 +4328,11 @@ static int si_vm_packet3_compute_check(s
+ return -EINVAL;
+ }
+ break;
++ case PACKET3_CP_DMA:
++ r = si_vm_packet3_cp_dma_check(ib, idx);
++ if (r)
++ return r;
++ break;
+ default:
+ DRM_ERROR("Invalid Compute packet3: 0x%x\n", pkt->opcode);
+ return -EINVAL;
+--- a/include/uapi/drm/radeon_drm.h
++++ b/include/uapi/drm/radeon_drm.h
+@@ -979,6 +979,8 @@ struct drm_radeon_cs {
+ #define RADEON_INFO_RING_WORKING 0x15
+ /* SI tile mode array */
+ #define RADEON_INFO_SI_TILE_MODE_ARRAY 0x16
++/* query if CP DMA is supported on the compute ring */
++#define RADEON_INFO_SI_CP_DMA_COMPUTE 0x17
+
+
+ struct drm_radeon_info {
--- /dev/null
+From 0b31e02363b0db4e7931561bc6c141436e729d9f Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Mon, 19 Aug 2013 11:06:50 -0400
+Subject: drm/radeon: update line buffer allocation for dce4.1/5
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit 0b31e02363b0db4e7931561bc6c141436e729d9f upstream.
+
+We need to allocate line buffer to each display when
+setting up the watermarks. Failure to do so can lead
+to a blank screen. This fixes blank screen problems
+on dce4.1/5 asics.
+
+Based on an initial fix from:
+Jay Cornwall <jay.cornwall@amd.com>
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/evergreen.c | 25 +++++++++++++++++++++----
+ drivers/gpu/drm/radeon/evergreend.h | 4 ++++
+ 2 files changed, 25 insertions(+), 4 deletions(-)
+
+--- a/drivers/gpu/drm/radeon/evergreen.c
++++ b/drivers/gpu/drm/radeon/evergreen.c
+@@ -1807,7 +1807,8 @@ static u32 evergreen_line_buffer_adjust(
+ struct drm_display_mode *mode,
+ struct drm_display_mode *other_mode)
+ {
+- u32 tmp;
++ u32 tmp, buffer_alloc, i;
++ u32 pipe_offset = radeon_crtc->crtc_id * 0x20;
+ /*
+ * Line Buffer Setup
+ * There are 3 line buffers, each one shared by 2 display controllers.
+@@ -1830,18 +1831,34 @@ static u32 evergreen_line_buffer_adjust(
+ * non-linked crtcs for maximum line buffer allocation.
+ */
+ if (radeon_crtc->base.enabled && mode) {
+- if (other_mode)
++ if (other_mode) {
+ tmp = 0; /* 1/2 */
+- else
++ buffer_alloc = 1;
++ } else {
+ tmp = 2; /* whole */
+- } else
++ buffer_alloc = 2;
++ }
++ } else {
+ tmp = 0;
++ buffer_alloc = 0;
++ }
+
+ /* second controller of the pair uses second half of the lb */
+ if (radeon_crtc->crtc_id % 2)
+ tmp += 4;
+ WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp);
+
++ if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
++ WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
++ DMIF_BUFFERS_ALLOCATED(buffer_alloc));
++ for (i = 0; i < rdev->usec_timeout; i++) {
++ if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
++ DMIF_BUFFERS_ALLOCATED_COMPLETED)
++ break;
++ udelay(1);
++ }
++ }
++
+ if (radeon_crtc->base.enabled && mode) {
+ switch (tmp) {
+ case 0:
+--- a/drivers/gpu/drm/radeon/evergreend.h
++++ b/drivers/gpu/drm/radeon/evergreend.h
+@@ -1153,6 +1153,10 @@
+ # define LATENCY_LOW_WATERMARK(x) ((x) << 0)
+ # define LATENCY_HIGH_WATERMARK(x) ((x) << 16)
+
++#define PIPE0_DMIF_BUFFER_CONTROL 0x0ca0
++# define DMIF_BUFFERS_ALLOCATED(x) ((x) << 0)
++# define DMIF_BUFFERS_ALLOCATED_COMPLETED (1 << 4)
++
+ #define IH_RB_CNTL 0x3e00
+ # define IH_RB_ENABLE (1 << 0)
+ # define IH_IB_SIZE(x) ((x) << 1) /* log2 */
--- /dev/null
+From 290d24576ccf1aa0373d2185cedfe262d0d4952a Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Mon, 19 Aug 2013 11:15:43 -0400
+Subject: drm/radeon: update line buffer allocation for dce6
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit 290d24576ccf1aa0373d2185cedfe262d0d4952a upstream.
+
+We need to allocate line buffer to each display when
+setting up the watermarks. Failure to do so can lead
+to a blank screen. This fixes blank screen problems
+on dce6 asics.
+
+Fixes:
+https://bugs.freedesktop.org/show_bug.cgi?id=64850
+
+Based on an initial fix from:
+Jay Cornwall <jay.cornwall@amd.com>
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/si.c | 23 +++++++++++++++++++----
+ drivers/gpu/drm/radeon/sid.h | 4 ++++
+ 2 files changed, 23 insertions(+), 4 deletions(-)
+
+--- a/drivers/gpu/drm/radeon/si.c
++++ b/drivers/gpu/drm/radeon/si.c
+@@ -1704,7 +1704,8 @@ static u32 dce6_line_buffer_adjust(struc
+ struct drm_display_mode *mode,
+ struct drm_display_mode *other_mode)
+ {
+- u32 tmp;
++ u32 tmp, buffer_alloc, i;
++ u32 pipe_offset = radeon_crtc->crtc_id * 0x20;
+ /*
+ * Line Buffer Setup
+ * There are 3 line buffers, each one shared by 2 display controllers.
+@@ -1719,16 +1720,30 @@ static u32 dce6_line_buffer_adjust(struc
+ * non-linked crtcs for maximum line buffer allocation.
+ */
+ if (radeon_crtc->base.enabled && mode) {
+- if (other_mode)
++ if (other_mode) {
+ tmp = 0; /* 1/2 */
+- else
++ buffer_alloc = 1;
++ } else {
+ tmp = 2; /* whole */
+- } else
++ buffer_alloc = 2;
++ }
++ } else {
+ tmp = 0;
++ buffer_alloc = 0;
++ }
+
+ WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset,
+ DC_LB_MEMORY_CONFIG(tmp));
+
++ WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
++ DMIF_BUFFERS_ALLOCATED(buffer_alloc));
++ for (i = 0; i < rdev->usec_timeout; i++) {
++ if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
++ DMIF_BUFFERS_ALLOCATED_COMPLETED)
++ break;
++ udelay(1);
++ }
++
+ if (radeon_crtc->base.enabled && mode) {
+ switch (tmp) {
+ case 0:
+--- a/drivers/gpu/drm/radeon/sid.h
++++ b/drivers/gpu/drm/radeon/sid.h
+@@ -282,6 +282,10 @@
+
+ #define DMIF_ADDR_CALC 0xC00
+
++#define PIPE0_DMIF_BUFFER_CONTROL 0x0ca0
++# define DMIF_BUFFERS_ALLOCATED(x) ((x) << 0)
++# define DMIF_BUFFERS_ALLOCATED_COMPLETED (1 << 4)
++
+ #define SRBM_STATUS 0xE50
+ #define GRBM_RQ_PENDING (1 << 5)
+ #define VMC_BUSY (1 << 8)
drm-radeon-fix-init-ordering-for-r600.patch
drm-radeon-cik-update-gpu_init-for-an-additional-berlin-gpu.patch
drm-radeon-add-berlin-pci-ids.patch
+drm-radeon-si-add-support-for-cp-dma-to-cs-checker-for-compute-v2.patch
+drm-radeon-update-line-buffer-allocation-for-dce4.1-5.patch
+drm-radeon-update-line-buffer-allocation-for-dce6.patch
+drm-radeon-fix-resume-on-some-rs4xx-boards-v2.patch
+drm-radeon-fix-handling-of-variable-sized-arrays-for-router-objects.patch
+drm-radeon-dpm-make-sure-dc-performance-level-limits-are-valid-btc-si-v2.patch
projects / thirdparty / kernel / stable-queue.git / commitdiff
