F: configs/rpi_*
T: git https://source.denx.de/u-boot/custodians/u-boot-arm.git
+ARM BROADCOM BCMBCA
+M: Anand Gore <anand.gore@broadcom.com>
+M: William Zhang <william.zhang@broadcom.com>
+M: Kursad Oney <kursad.oney@broadcom.com>
+M: Joel Peshkin <joel.peshkin@broadcom.com>
+S: Maintained
+F: arch/arm/mach-bcmbca/
+F: board/broadcom/bcmbca/
+F: configs/bcm947622_defconfig
+F: include/configs/bcm947622.h
+
ARM BROADCOM BCMSTB
M: Thomas Fitzsimmons <fitzsim@fitzsim.org>
S: Maintained
F: arch/arm/include/asm/arch-hi6220/
F: arch/arm/include/asm/arch-hi3660/
+ARM HPE GXP ARCHITECTURE
+M: Jean-Marie Verdun <verdun@hpe.com>
+M: Nick Hawkins <nick.hawkins@hpe.com>
+S: Maintained
+F: arch/arm/dts/hpe-bmc*
+F: arch/arm/dts/hpe-gxp*
+F: arch/arm/mach-hpe/
+F: board/hpe/
+F: configs/gxp_defconfig
+F: doc/device-tree-bindings/spi/hpe,gxp-spi.yaml
+F: drivers/timer/gxp-timer.c
+F: drivers/spi/gxp_spi.c
+
ARM IPQ40XX
M: Robert Marko <robert.marko@sartura.hr>
M: Luka Kovacic <luka.kovacic@sartura.hr>
F: drivers/net/mdio-ipq4019.c
F: drivers/rng/msm_rng.c
+ARM LAYERSCAPE SFP
+M: Sean Anderson <sean.anderson@seco.com>
+S: Maintained
+F: drivers/misc/ls2_sfp.c
+
ARM MARVELL KIRKWOOD ARMADA-XP ARMADA-38X ARMADA-37XX ARMADA-7K/8K
M: Stefan Roese <sr@denx.de>
S: Maintained
F: arch/arm/mach-stm32mp/
F: doc/board/st/
F: drivers/adc/stm32-adc*
-F: drivers/clk/clk_stm32mp1.c
+F: drivers/clk/stm32/
F: drivers/gpio/stm32_gpio.c
F: drivers/hwspinlock/stm32_hwspinlock.c
F: drivers/i2c/stm32f7_i2c.c
F: drivers/serial/serial_xuartlite.c
F: drivers/spi/xilinx_spi.c
F: drivers/sysreset/sysreset_gpio.c
+ F: drivers/timer/xilinx-timer.c
F: drivers/watchdog/xilinx_tb_wdt.c
N: xilinx
F: include/nvme.h
F: doc/develop/driver-model/nvme.rst
+NVMEM
+M: Sean Anderson <seanga2@gmail.com>
+S: Maintained
+F: doc/api/nvmem.rst
+F: drivers/misc/nvmem.c
+F: include/nvmem.h
+
NXP C45 TJA11XX PHY DRIVER
M: Radu Pirea <radu-nicolae.pirea@oss.nxp.com>
S: Maintained
F: drivers/misc/sl28cpld.c
F: drivers/watchdog/sl28cpld-wdt.c
+SMCCC TRNG
+M: Etienne Carriere <etienne.carriere@linaro.org>
+S: Maintained
+F: drivers/rng/smccc_trng.c
+
SPI
M: Jagan Teki <jagan@amarulasolutions.com>
S: Maintained
VERSION = 2022
PATCHLEVEL = 07
SUBLEVEL =
-EXTRAVERSION = -rc4
+EXTRAVERSION = -rc5
NAME =
# *DOCUMENTATION*
# the raw binary, but certain simulators only accept an ELF file (but don't
# do the relocation).
ifneq ($(CONFIG_STATIC_RELA),)
- # $(1) is u-boot ELF, $(2) is u-boot bin, $(3) is text base
+ # $(2) is u-boot ELF, $(3) is u-boot bin, $(4) is text base
quiet_cmd_static_rela = RELOC $@
cmd_static_rela = \
- start=$$($(NM) $(2) | grep __rel_dyn_start | cut -f 1 -d ' '); \
- end=$$($(NM) $(2) | grep __rel_dyn_end | cut -f 1 -d ' '); \
- tools/relocate-rela $(3) $(4) $$start $$end
+ tools/relocate-rela $(3) $(2)
else
quiet_cmd_static_rela =
cmd_static_rela =
config HAVE_ARCH_IOREMAP
bool
- config NEEDS_MANUAL_RELOC
- bool
-
config SYS_CACHE_SHIFT_4
bool
config MICROBLAZE
bool "MicroBlaze architecture"
- select NEEDS_MANUAL_RELOC
select SUPPORT_OF_CONTROL
- imply CMD_IRQ
+ imply CMD_TIMER
+ imply SPL_REGMAP if SPL
+ imply SPL_TIMER if SPL
+ imply TIMER
+ imply XILINX_TIMER
config MIPS
bool "MIPS architecture"
select BZIP2
select CMD_POWEROFF
select DM
+ select DM_FUZZING_ENGINE
select DM_GPIO
select DM_I2C
select DM_KEYBOARD
imply CRC32_VERIFY
imply FAT_WRITE
imply FIRMWARE
+ imply FUZZING_ENGINE_SANDBOX
imply HASH_VERIFY
imply LZMA
imply TEE
default 0xF0000000 if ARCH_MPC8313
default 0xE0000000 if MPC83xx && !ARCH_MPC8313
default 0x01000000 if ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
+ default 0xFFE00000 if ARCH_P1010 || ARCH_P1011 || ARCH_P1020 || \
+ ARCH_P1021 || ARCH_P1024 || ARCH_P1025 || \
+ ARCH_P2020
default SYS_CCSRBAR_DEFAULT
help
Address for the Internal Memory-Mapped Registers (IMMR) window used
source "arch/riscv/Kconfig"
source "board/keymile/Kconfig"
+
+ if MIPS || MICROBLAZE
+
+ choice
+ prompt "Endianness selection"
+ help
+ Some MIPS boards can be configured for either little or big endian
+ byte order. These modes require different U-Boot images. In general there
+ is one preferred byteorder for a particular system but some systems are
+ just as commonly used in the one or the other endianness.
+
+ config SYS_BIG_ENDIAN
+ bool "Big endian"
+ depends on (SUPPORTS_BIG_ENDIAN && MIPS) || MICROBLAZE
+
+ config SYS_LITTLE_ENDIAN
+ bool "Little endian"
+ depends on (SUPPORTS_LITTLE_ENDIAN && MIPS) || MICROBLAZE
+
+ endchoice
+
+ endif
zynqmp-mini-qspi.dtb \
zynqmp-sm-k26-revA.dtb \
zynqmp-smk-k26-revA.dtb \
+ zynqmp-sck-kr-g-revA.dtbo \
+ zynqmp-sck-kr-g-revB.dtbo \
zynqmp-sck-kv-g-revA.dtbo \
zynqmp-sck-kv-g-revB.dtbo \
zynqmp-topic-miamimp-xilinx-xdp-v1r1.dtb \
omap3-beagle-xm.dtb \
omap3-beagle.dtb
+dtb-$(CONFIG_TARGET_DEVKIT8000) += omap3-devkit8000.dtb
+
dtb-$(CONFIG_TARGET_OMAP3_IGEP00X0) += \
omap3-igep0020.dtb
dtb-$(CONFIG_ARCH_BCMSTB) += bcm7xxx.dtb
+dtb-$(CONFIG_BCM47622) += \
+ bcm947622.dtb
+
dtb-$(CONFIG_ASPEED_AST2500) += ast2500-evb.dtb
dtb-$(CONFIG_ASPEED_AST2600) += ast2600-evb.dtb
dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb
+dtb-$(CONFIG_STM32MP13x) += \
+ stm32mp135f-dk.dtb
+
dtb-$(CONFIG_STM32MP15x) += \
stm32mp157a-dk1.dtb \
stm32mp157a-icore-stm32mp1-ctouch2.dtb \
stm32mp15xx-dhcom-drc02.dtb \
stm32mp15xx-dhcom-pdk2.dtb \
stm32mp15xx-dhcom-picoitx.dtb \
- stm32mp15xx-dhcor-avenger96.dtb
+ stm32mp15xx-dhcor-avenger96.dtb \
+ stm32mp15xx-dhcor-drc-compact.dtb
dtb-$(CONFIG_SOC_K3_AM6) += \
k3-am654-base-board.dtb \
k3-am642-sk.dtb \
k3-am642-r5-sk.dtb
+dtb-$(CONFIG_SOC_K3_AM625) += k3-am625-sk.dtb \
+ k3-am625-r5-sk.dtb
+
dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt7622-rfb.dtb \
mt7623a-unielec-u7623-02-emmc.dtb \
dtb-$(CONFIG_TARGET_PRESIDIO_ASIC) += ca-presidio-engboard.dtb
+dtb-$(CONFIG_TARGET_GXP) += hpe-bmc-dl360gen10.dts
+
dtb-$(CONFIG_TARGET_IMX8MM_CL_IOT_GATE) += imx8mm-cl-iot-gate.dtb \
imx8mm-cl-iot-gate-ied.dtbo \
imx8mm-cl-iot-gate-ied-adc0.dtbo \
dtb-$(CONFIG_ARCH_QEMU) += qemu-arm.dtb qemu-arm64.dtb
+dtb-$(CONFIG_TARGET_CORSTONE1000) += corstone1000-mps3.dtb \
+ corstone1000-fvp.dtb
+
include $(srctree)/scripts/Makefile.dts
targets += $(dtb-y)
config SYS_ARCH
default "m68k"
+ config NEEDS_MANUAL_RELOC
+ def_bool y
+
# processor family
config MCF520x
select OF_CONTROL
select DM_SERIAL
bool
-config MCF5227x
- select OF_CONTROL
- select DM
- select DM_SERIAL
- bool
-
# processor type
config M5208
bool
#include <asm-offsets.h>
#include <config.h>
+ #if defined(CONFIG_STATIC_RELA)
+ #define SYM_ADDR(reg, reg_add, symbol) \
+ mfs r20, rpc; \
+ addik r20, r20, _GLOBAL_OFFSET_TABLE_ + 8; \
+ lwi reg, r20, symbol@GOT; \
+ addk reg, reg reg_add;
+ #else
+ #define SYM_ADDR(reg, reg_add, symbol) \
+ addi reg, reg_add, symbol
+ #endif
+
.text
.global _start
_start:
mts rmsr, r0 /* disable cache */
+ mfs r20, rpc
+ addi r20, r20, -4
- addi r8, r0, _end
- mts rslr, r8
+ mts rslr, r0
+ mts rshr, r20
#if defined(CONFIG_SPL_BUILD)
- addi r1, r0, CONFIG_SPL_STACK_ADDR
+ addi r1, r0, CONFIG_SPL_STACK
#else
- addi r1, r0, CONFIG_SYS_INIT_SP_OFFSET
+ add r1, r0, r20
+ #if defined(CONFIG_STATIC_RELA)
+ bri 1f
+
+ /* Force alignment for easier ASM code below */
+ #define ALIGNMENT_ADDR 0x20
+ .align 4
+ uboot_dyn_start:
+ .word __rel_dyn_start
+
+ uboot_dyn_end:
+ .word __rel_dyn_end
+
+ uboot_sym_start:
+ .word __dyn_sym_start
+ 1:
+
+ addi r5, r20, 0
+ add r6, r0, r0
+
+ lwi r7, r20, ALIGNMENT_ADDR
+ addi r7, r7, -CONFIG_SYS_TEXT_BASE
+ add r7, r7, r5
+ lwi r8, r20, ALIGNMENT_ADDR + 0x4
+ addi r8, r8, -CONFIG_SYS_TEXT_BASE
+ add r8, r8, r5
+ lwi r9, r20, ALIGNMENT_ADDR + 0x8
+ addi r9, r9, -CONFIG_SYS_TEXT_BASE
+ add r9, r9, r5
+ addi r10, r0, CONFIG_SYS_TEXT_BASE
+
+ brlid r15, mb_fix_rela
+ nop
+ #endif
#endif
addi r1, r1, -4 /* Decrement SP to top of memory */
/* Call board_init_f_alloc_reserve with the current stack pointer as
* parameter. */
add r5, r0, r1
- bralid r15, board_init_f_alloc_reserve
+ brlid r15, board_init_f_alloc_reserve
nop
/* board_init_f_alloc_reserve returns a pointer to the allocated area
/* Call board_init_f_init_reserve with the address returned by
* board_init_f_alloc_reserve as parameter. */
add r5, r0, r3
- bralid r15, board_init_f_init_reserve
+ brlid r15, board_init_f_init_reserve
nop
#if !defined(CONFIG_SPL_BUILD)
/* Setup vectors with pre-relocation symbols */
or r5, r0, r0
- bralid r15, __setup_exceptions
+ brlid r15, __setup_exceptions
nop
#endif
+ /*
+ * Initialize global data cpuinfo with default values (cache
+ * size, cache line size, etc).
+ */
+ brlid r15, microblaze_early_cpuinfo_init
+ nop
+
/* Flush cache before enable cache */
- addik r5, r0, 0
- addik r6, r0, XILINX_DCACHE_BYTE_SIZE
- bralid r15, flush_cache
+ brlid r15, flush_cache_all
nop
/* enable instruction and data cache */
clear_bss:
/* clear BSS segments */
- addi r5, r0, __bss_start
- addi r4, r0, __bss_end
+ SYM_ADDR(r5, r0, __bss_start)
+ SYM_ADDR(r4, r0, __bss_end)
cmp r6, r5, r4
beqi r6, 3f
2:
bnei r6, 2b
3: /* jumping to board_init */
#ifdef CONFIG_DEBUG_UART
- bralid r15, debug_uart_init
+ brlid r15, debug_uart_init
nop
#endif
#ifndef CONFIG_SPL_BUILD
or r5, r0, r0 /* flags - empty */
- brai board_init_f
+ bri board_init_f
#else
- brai board_init_r
+ bri board_init_r
#endif
1: bri 1b
swi r2, r4, 0x0 /* reset address - imm opcode */
swi r3, r4, 0x4 /* reset address - brai opcode */
- addik r6, r0, CONFIG_SYS_TEXT_BASE
+ SYM_ADDR(r6, r0, _start)
+ /* Intentionally keep reset vector back to origin u-boot location */
sw r6, r1, r0
lhu r7, r1, r10
rsubi r8, r10, 0x2
swi r2, r4, 0x8 /* user vector exception - imm opcode */
swi r3, r4, 0xC /* user vector exception - brai opcode */
- addik r6, r5, _exception_handler
+ SYM_ADDR(r6, r5, _exception_handler)
sw r6, r1, r0
/*
* BIG ENDIAN memory map for user exception
swi r2, r4, 0x10 /* interrupt - imm opcode */
swi r3, r4, 0x14 /* interrupt - brai opcode */
- addik r6, r5, _interrupt_handler
+ SYM_ADDR(r6, r5, _interrupt_handler)
sw r6, r1, r0
lhu r7, r1, r10
rsubi r8, r10, 0x12
swi r2, r4, 0x20 /* hardware exception - imm opcode */
swi r3, r4, 0x24 /* hardware exception - brai opcode */
- addik r6, r5, _hw_exception_handler
+ SYM_ADDR(r6, r5, _hw_exception_handler)
sw r6, r1, r0
lhu r7, r1, r10
rsubi r8, r10, 0x22
or r0, r0, r0
.end __setup_exceptions
- /*
- * Read 16bit little endian
- */
- .text
- .global in16
- .ent in16
- .align 2
- in16: lhu r3, r0, r5
- bslli r4, r3, 8
- bsrli r3, r3, 8
- andi r4, r4, 0xffff
- or r3, r3, r4
- rtsd r15, 8
- sext16 r3, r3
- .end in16
-
- /*
- * Write 16bit little endian
- * first parameter(r5) - address, second(r6) - short value
- */
- .text
- .global out16
- .ent out16
- .align 2
- out16: bslli r3, r6, 8
- bsrli r6, r6, 8
- andi r3, r3, 0xffff
- or r3, r3, r6
- sh r3, r0, r5
- rtsd r15, 8
- or r0, r0, r0
- .end out16
-
/*
* Relocate u-boot
*/
* r7 - reloc_addr
*/
addi r1, r5, 0 /* Start to use new SP */
+ mts rshr, r1
addi r31, r6, 0 /* Start to use new GD */
- add r23, r0, r7 /* Move reloc addr to r23 */
/* Relocate text and data - r12 temp value */
- addi r21, r0, _start
- addi r22, r0, _end - 4 /* Include BSS too */
+ SYM_ADDR(r21, r0, _start)
+ SYM_ADDR(r22, r0, _end) /* Include BSS too */
+ addi r22, r22, -4
rsub r6, r21, r22
or r5, r0, r0
1: lw r12, r21, r5 /* Load u-boot data */
- sw r12, r23, r5 /* Write zero to loc */
+ sw r12, r7, r5 /* Write zero to loc */
cmp r12, r5, r6 /* Check if we have reach the end */
bneid r12, 1b
addi r5, r5, 4 /* Increment to next loc - relocate code */
/* R23 points to the base address. */
- add r23, r0, r7 /* Move reloc addr to r23 */
- addi r24, r0, CONFIG_SYS_TEXT_BASE /* Get reloc offset */
- rsub r23, r24, r23 /* keep - this is already here gd->reloc_off */
+ rsub r23, r21, r7 /* keep - this is already here gd->reloc_off */
/* Setup vectors with post-relocation symbols */
add r5, r0, r23 /* load gd->reloc_off to r5 */
- bralid r15, __setup_exceptions
+ brlid r15, __setup_exceptions
+ nop
+
+ #if defined(CONFIG_STATIC_RELA)
+ /* reloc_offset is current location */
+ SYM_ADDR(r10, r0, _start)
+
+ /* r5 new address where I should copy code */
+ add r5, r0, r7 /* Move reloc addr to r5 */
+
+ /* Verbose message */
+ addi r6, r0, 0
+
+ SYM_ADDR(r7, r0, __rel_dyn_start)
+ rsub r7, r10, r7
+ add r7, r7, r5
+ SYM_ADDR(r8, r0, __rel_dyn_end)
+ rsub r8, r10, r8
+ add r8, r8, r5
+ SYM_ADDR(r9, r0, __dyn_sym_start)
+ rsub r9, r10, r9
+ add r9, r9, r5
+ brlid r15, mb_fix_rela
nop
+ /* end of code which does relocation */
+ #else
/* Check if GOT exist */
addik r21, r23, _got_start
addik r22, r23, _got_end
cmpu r12, r21, r22 /* Check if this cross boundary */
bneid r12, 3b
addik r21. r21, 4
-
- /* Update pointer to GOT */
- mfs r20, rpc
- addik r20, r20, _GLOBAL_OFFSET_TABLE_ + 8
- addk r20, r20, r23
+ #endif
/* Flush caches to ensure consistency */
- addik r5, r0, 0
- addik r6, r0, XILINX_DCACHE_BYTE_SIZE
- bralid r15, flush_cache
+ brlid r15, flush_cache_all
nop
2: addi r5, r31, 0 /* gd is initialized in board_r.c */
- addi r6, r0, CONFIG_SYS_TEXT_BASE
- addi r12, r23, board_init_r
+ SYM_ADDR(r6, r0, _start)
+ SYM_ADDR(r12, r23, board_init_r)
bra r12 /* Jump to relocated code */
.end relocate_code
}
. = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
+ __u_boot_list : {
+ KEEP(*(SORT(__u_boot_list*)));
}
__init_end = . ;
+ . = ALIGN(4);
+ __rel_dyn_start = .;
+ .rela.dyn : {
+ *(.rela.dyn)
+ }
+ __rel_dyn_end = .;
+
+ . = ALIGN(4);
+ __dyn_sym_start = .;
+ .dynsym : {
+ *(.dynsym)
+ }
+ __dyn_sym_end = .;
+
.bss ALIGN(0x4):
{
__bss_start = .;
CONFIG_XILINX_MICROBLAZE0_USE_DIV=1
CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL=1
CONFIG_DISTRO_DEFAULTS=y
+ CONFIG_REMAKE_ELF=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_BOOTDELAY=-1
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_FOOTPRINT_LIMIT=y
+CONFIG_SPL_MAX_FOOTPRINT=0xffb00
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_STACK=0x100000
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
+CONFIG_SYS_SPL_ARGS_ADDR=0x2a000000
CONFIG_SYS_OS_BASE=0x2c060000
CONFIG_SYS_PROMPT="U-Boot-mONStR> "
+CONFIG_SYS_MAXARGS=15
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=544
CONFIG_CMD_IMLS=y
CONFIG_CMD_SPL=y
CONFIG_CMD_ASKENV=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_VITESSE=y
CONFIG_DM_ETH=y
+ CONFIG_DM_ETH_PHY=y
CONFIG_XILINX_AXIEMAC=y
CONFIG_XILINX_EMACLITE=y
CONFIG_SYS_NS16550=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_CLOCKS=y
CONFIG_SYS_PROMPT="Versal> "
+CONFIG_SYS_MAXARGS=64
+CONFIG_SYS_PBSIZE=2073
CONFIG_CMD_BOOTMENU=y
CONFIG_CMD_NVEDIT_EFI=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_EXT4_WRITE=y
+ CONFIG_CMD_SQUASHFS=y
CONFIG_CMD_MTDPARTS=y
CONFIG_CMD_UBI=y
CONFIG_PARTITION_TYPE_GUID=y
CONFIG_PHY_TI_DP83867=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_FIXED=y
+ CONFIG_DM_ETH_PHY=y
CONFIG_PHY_GIGE=y
CONFIG_XILINX_AXIEMAC=y
CONFIG_XILINX_AXIMRMAC=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_USE_PREBOOT=y
CONFIG_CLOCKS=y
+CONFIG_SPL_MAX_SIZE=0x30000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x100000
+CONFIG_SPL_BSS_MAX_SIZE=0x100000
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_STACK=0xfffffe00
CONFIG_SPL_STACK_R=y
+CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SYS_SPL_MALLOC_SIZE=0x2000000
+CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
+CONFIG_SPL_FS_LOAD_ARGS_NAME="system.dtb"
CONFIG_SPL_FPGA=y
CONFIG_SPL_OS_BOOT=y
+CONFIG_SYS_SPL_ARGS_ADDR=0x10000000
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
+CONFIG_SYS_MAXARGS=32
+CONFIG_SYS_PBSIZE=2071
# CONFIG_BOOTM_NETBSD is not set
CONFIG_CMD_IMLS=y
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_EXT4_WRITE=y
+ CONFIG_CMD_SQUASHFS=y
CONFIG_CMD_MTDPARTS=y
CONFIG_CMD_MTDPARTS_SPREAD=y
CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_XILINX=y
+ CONFIG_DM_ETH_PHY=y
CONFIG_MII=y
CONFIG_ZYNQ_GEM=y
CONFIG_ARM_DCC=y
CONFIG_PREBOOT="run scsi_init;usb start"
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_CLOCKS=y
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x0
+CONFIG_SPL_BSS_MAX_SIZE=0x80000
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_STACK=0xfffffffc
CONFIG_SPL_STACK_R=y
+CONFIG_SYS_SPL_MALLOC=y
+CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
+CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x20000000
+CONFIG_SYS_SPL_MALLOC_SIZE=0x1000000
+CONFIG_SPL_FS_LOAD_KERNEL_NAME="atf-uboot.ub"
+CONFIG_SPL_FS_LOAD_ARGS_NAME="u-boot.bin"
CONFIG_SPL_FPGA=y
CONFIG_SPL_OS_BOOT=y
+CONFIG_SYS_SPL_ARGS_ADDR=0x8000000
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
CONFIG_SPL_ATF=y
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
+CONFIG_SYS_MAXARGS=64
+CONFIG_SYS_PBSIZE=2073
CONFIG_CMD_BOOTMENU=y
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_NVEDIT_EFI=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_TPM=y
CONFIG_CMD_EXT4_WRITE=y
+ CONFIG_CMD_SQUASHFS=y
CONFIG_CMD_MTDPARTS=y
CONFIG_CMD_MTDPARTS_SPREAD=y
CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_XILINX_GMII2RGMII=y
CONFIG_PHY_FIXED=y
+ CONFIG_DM_ETH_PHY=y
CONFIG_XILINX_AXIEMAC=y
CONFIG_ZYNQ_GEM=y
CONFIG_DM_REGULATOR=y
* within this range at the start. The driver can then
* use normal flush-after-write, invalidate-before-read
* procedures.
- *
- * TODO(sjg@chromium.org): Drop this microblaze
- * exception.
*/
- #ifndef CONFIG_MICROBLAZE
flush_dcache_range((ulong)priv, (ulong)priv + size);
- #endif
}
} else {
priv = calloc(1, size);
bool of_machine_is_compatible(const char *compat)
{
- const void *fdt = gd->fdt_blob;
-
- return !fdt_node_check_compatible(fdt, 0, compat);
+ return ofnode_device_is_compatible(ofnode_root(), compat);
}
int dev_disable_by_path(const char *path)
Enables support for the Designware APB Timer driver. This timer is
present on Altera SoCFPGA SoCs.
+config GXP_TIMER
+ bool "HPE GXP Timer"
+ depends on TIMER
+ help
+ Enables support for the GXP Timer driver. This timer is
+ present on HPE GXP SoCs.
+
config MPC83XX_TIMER
bool "MPC83xx timer support"
depends on TIMER
Select this to enable support for the timer found on
NXP i.MX devices.
+ config XILINX_TIMER
+ bool "Xilinx timer support"
+ depends on TIMER
+ select REGMAP
+ select SPL_REGMAP if SPL
+ help
+ Select this to enable support for the timer found on
+ any Xilinx boards (axi timer).
+
endmenu
obj-$(CONFIG_$(SPL_)ATMEL_TCB_TIMER) += atmel_tcb_timer.o
obj-$(CONFIG_CADENCE_TTC_TIMER) += cadence-ttc.o
obj-$(CONFIG_DESIGNWARE_APB_TIMER) += dw-apb-timer.o
+obj-$(CONFIG_GXP_TIMER) += gxp-timer.o
obj-$(CONFIG_MPC83XX_TIMER) += mpc83xx_timer.o
obj-$(CONFIG_NOMADIK_MTU_TIMER) += nomadik-mtu-timer.o
obj-$(CONFIG_NPCM_TIMER) += npcm-timer.o
obj-$(CONFIG_MTK_TIMER) += mtk_timer.o
obj-$(CONFIG_MCHP_PIT64B_TIMER) += mchp-pit64b-timer.o
obj-$(CONFIG_IMX_GPT_TIMER) += imx-gpt-timer.o
+ obj-$(CONFIG_XILINX_TIMER) += xilinx-timer.o
# define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
- /* Stack location before relocation */
- #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_TEXT_BASE - \
- CONFIG_SYS_MALLOC_F_LEN)
-
#ifdef CONFIG_CFI_FLASH
/* ?empty sector */
# define CONFIG_SYS_FLASH_EMPTY_INFO 1
# define CONFIG_SYS_MAX_FLASH_SECT 2048
#endif
- #ifndef XILINX_DCACHE_BYTE_SIZE
- #define XILINX_DCACHE_BYTE_SIZE 32768
- #endif
-/* size of console buffer */
-#define CONFIG_SYS_CBSIZE 512
-/* max number of command args */
-#define CONFIG_SYS_MAXARGS 15
--
#define CONFIG_HOSTNAME "microblaze-generic"
/* architecture dependent code */
#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE
-/* for booting directly linux */
-#define CONFIG_SYS_FDT_BASE (CONFIG_SYS_TEXT_BASE + \
- 0x40000)
-
-#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_TEXT_BASE + \
- 0x1000000)
-
/* SP location before relocation, must use scratch RAM */
/* BRAM start */
#define CONFIG_SYS_INIT_RAM_ADDR 0x0
/* BRAM size - will be generated */
#define CONFIG_SYS_INIT_RAM_SIZE 0x100000
-# define CONFIG_SPL_STACK_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE)
-
-/* Just for sure that there is a space for stack */
-#define CONFIG_SPL_STACK_SIZE 0x100
-
-#define CONFIG_SPL_MAX_FOOTPRINT (CONFIG_SYS_INIT_RAM_SIZE - \
- CONFIG_SYS_INIT_RAM_ADDR - \
- CONFIG_SYS_MALLOC_F_LEN - \
- CONFIG_SPL_STACK_SIZE)
-
#endif /* __CONFIG_H */
projects / thirdparty / u-boot.git / commitdiff
