]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
ARM: dts: imx6qdl-tqma6: add boot phase properties
authorMax Merchel <Max.Merchel@ew.tq-group.com>
Fri, 20 Feb 2026 14:30:04 +0000 (15:30 +0100)
committerFrank Li <Frank.Li@nxp.com>
Mon, 6 Apr 2026 01:35:27 +0000 (21:35 -0400)
dtschema/schemas/bootph.yaml describe various node usage during
boot phases with DT.

TQMa6 need eMMC, I2C, GPIO, regulator and QSPI access during
boot process.

Signed-off-by: Max Merchel <Max.Merchel@ew.tq-group.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6.dtsi
arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6a.dtsi
arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6b.dtsi

index 07492f63a1f801e1166346049074a5d019fa6219..14676d1d905a185d68c8ceb9680beed6a95311e3 100644 (file)
@@ -11,6 +11,7 @@
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_ecspi1>;
        cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
+       bootph-pre-ram;
        status = "okay";
 
        m25p80: flash@0 {
@@ -19,6 +20,7 @@
                spi-max-frequency = <50000000>;
                vcc-supply = <&sw4_reg>;
                m25p,fast-read;
+               bootph-pre-ram;
 
                partitions {
                        compatible = "fixed-partitions";
        };
 };
 
+&gpio3 {
+       bootph-pre-ram;
+};
+
 &iomuxc {
        pinctrl_ecspi1: ecspi1grp {
                fsl,pins = <
@@ -38,6 +44,7 @@
                         /* eCSPI1 SS1 */
                        MX6QDL_PAD_EIM_D19__GPIO3_IO19 0xb099
                >;
+               bootph-pre-ram;
        };
 
        pinctrl_i2c1: i2c1grp {
@@ -45,6 +52,7 @@
                        MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b899
                        MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b899
                >;
+               bootph-pre-ram;
        };
 
        pinctrl_i2c1_recovery: i2c1recoverygrp {
@@ -73,6 +81,7 @@
                        MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
                        MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
                >;
+               bootph-all;
        };
 };
 
                        regulator-min-microvolt = <3300000>;
                        regulator-max-microvolt = <3300000>;
                        regulator-always-on;
+                       bootph-pre-ram;
                };
 
                reg_5v_600mA: swbst {
        bus-width = <8>;
        #address-cells = <1>;
        #size-cells = <0>;
+       bootph-all;
        status = "okay";
 
        mmccard: mmccard@0 {
index 1251749a8dd003bdb36f4079fd73a8818084f7d2..67f8f59aff5aef567fd75a7dc991affa0be680db 100644 (file)
@@ -20,6 +20,7 @@
        scl-gpios = <&gpio5 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
        sda-gpios = <&gpio5 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
        clock-frequency = <100000>;
+       bootph-pre-ram;
        status = "okay";
 
        pmic: pmic@8 {
index 7f526f39e0f2bd4295898abd3323c6257f1c754f..db552802554d440a304dc355ed17c218083bd7cf 100644 (file)
@@ -13,6 +13,7 @@
        scl-gpios = <&gpio1 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
        sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
        clock-frequency = <100000>;
+       bootph-pre-ram;
        status = "okay";
 
        pmic: pmic@8 {
@@ -40,6 +41,7 @@
                        MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b899
                        MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b899
                >;
+               bootph-pre-ram;
        };
 
        pinctrl_i2c3_recovery: i2c3recoverygrp {