]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
ASoC: amd: acp: add ZSC control register programming sequence
authorVijendar Mukunda <Vijendar.Mukunda@amd.com>
Wed, 7 Aug 2024 08:51:48 +0000 (14:21 +0530)
committerMark Brown <broonie@kernel.org>
Thu, 8 Aug 2024 08:17:15 +0000 (09:17 +0100)
Add ZSC Control register programming sequence for ACP D0 and D3 state
transitions for ACP7.0 onwards. This will allow ACP to enter low power
state when ACP enters D3 state. When ACP enters D0 State, ZSC control
should be disabled.

Tested-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda@amd.com>
Link: https://patch.msgid.link/20240807085154.1987681-1-Vijendar.Mukunda@amd.com
Signed-off-by: Mark Brown <broonie@kernel.org>
sound/soc/amd/acp/acp-legacy-common.c
sound/soc/amd/acp/amd.h

index 4422cec81e3c4d351c5589ca451655f8b31b1ccd..04bd605fdce3d9282dffc79cbc089a7900d6c093 100644 (file)
@@ -321,6 +321,8 @@ int acp_init(struct acp_chip_info *chip)
                pr_err("ACP reset failed\n");
                return ret;
        }
+       if (chip->acp_rev >= ACP70_DEV)
+               writel(0, chip->base + ACP_ZSC_DSP_CTRL);
        return 0;
 }
 EXPORT_SYMBOL_NS_GPL(acp_init, SND_SOC_ACP_COMMON);
@@ -336,6 +338,9 @@ int acp_deinit(struct acp_chip_info *chip)
 
        if (chip->acp_rev != ACP70_DEV)
                writel(0, chip->base + ACP_CONTROL);
+
+       if (chip->acp_rev >= ACP70_DEV)
+               writel(0x01, chip->base + ACP_ZSC_DSP_CTRL);
        return 0;
 }
 EXPORT_SYMBOL_NS_GPL(acp_deinit, SND_SOC_ACP_COMMON);
index 87a4813783f911718bdb43814cda0d786f6691a4..c095a34a7229a6443d1d9e317e0fee5996874e85 100644 (file)
 #define ACP70_PGFSM_CONTROL                    ACP6X_PGFSM_CONTROL
 #define ACP70_PGFSM_STATUS                     ACP6X_PGFSM_STATUS
 
+#define ACP_ZSC_DSP_CTRL                       0x0001014
+#define ACP_ZSC_STS                            0x0001018
 #define ACP_SOFT_RST_DONE_MASK 0x00010001
 
 #define ACP_PGFSM_CNTL_POWER_ON_MASK            0xffffffff