6.3-stable patches

added patches:
	iommu-amd-pgtbl_v2-fix-domain-max-address.patch
	tpm-tpm_tis-request-threaded-interrupt-handler.patch

diff --git a/queue-6.3/iommu-amd-pgtbl_v2-fix-domain-max-address.patch b/queue-6.3/iommu-amd-pgtbl_v2-fix-domain-max-address.patch
new file mode 100644 (file)
index 0000000..544f6c1
--- /dev/null
+++ b/queue-6.3/iommu-amd-pgtbl_v2-fix-domain-max-address.patch
@@ -0,0 +1,59 @@
+From 11c439a19466e7feaccdbce148a75372fddaf4e9 Mon Sep 17 00:00:00 2001
+From: Vasant Hegde <vasant.hegde@amd.com>
+Date: Thu, 18 May 2023 05:43:51 +0000
+Subject: iommu/amd/pgtbl_v2: Fix domain max address
+
+From: Vasant Hegde <vasant.hegde@amd.com>
+
+commit 11c439a19466e7feaccdbce148a75372fddaf4e9 upstream.
+
+IOMMU v2 page table supports 4 level (47 bit) or 5 level (56 bit) virtual
+address space. Current code assumes it can support 64bit IOVA address
+space. If IOVA allocator allocates virtual address > 47/56 bit (depending
+on page table level) then it will do wrong mapping and cause invalid
+translation.
+
+Hence adjust aperture size to use max address supported by the page table.
+
+Reported-by: Jerry Snitselaar <jsnitsel@redhat.com>
+Fixes: aaac38f61487 ("iommu/amd: Initial support for AMD IOMMU v2 page table")
+Cc: <Stable@vger.kernel.org>  # v6.0+
+Cc: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
+Signed-off-by: Vasant Hegde <vasant.hegde@amd.com>
+Reviewed-by: Jerry Snitselaar <jsnitsel@redhat.com>
+Link: https://lore.kernel.org/r/20230518054351.9626-1-vasant.hegde@amd.com
+Signed-off-by: Joerg Roedel <jroedel@suse.de>
+[ Modified to work with "V2 with 4 level page table" only - Vasant ]
+Signed-off-by: Vasant Hegde <vasant.hegde@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/iommu/amd/iommu.c |   11 ++++++++++-
+ 1 file changed, 10 insertions(+), 1 deletion(-)
+
+--- a/drivers/iommu/amd/iommu.c
++++ b/drivers/iommu/amd/iommu.c
+@@ -2118,6 +2118,15 @@ out_err:
+       return NULL;
+ }
+ 
++static inline u64 dma_max_address(void)
++{
++      if (amd_iommu_pgtable == AMD_IOMMU_V1)
++              return ~0ULL;
++
++      /* V2 with 4 level page table */
++      return ((1ULL << PM_LEVEL_SHIFT(PAGE_MODE_4_LEVEL)) - 1);
++}
++
+ static struct iommu_domain *amd_iommu_domain_alloc(unsigned type)
+ {
+       struct protection_domain *domain;
+@@ -2134,7 +2143,7 @@ static struct iommu_domain *amd_iommu_do
+               return NULL;
+ 
+       domain->domain.geometry.aperture_start = 0;
+-      domain->domain.geometry.aperture_end   = ~0ULL;
++      domain->domain.geometry.aperture_end   = dma_max_address();
+       domain->domain.geometry.force_aperture = true;
+ 
+       return &domain->domain;

diff --git a/queue-6.3/series b/queue-6.3/series
index ef2d548cb9f205910105cf74ef6b2d0e0dd53f88..5d8e34d731b4974917564fcdff8c86719007ba25 100644 (file)
--- a/queue-6.3/series
+++ b/queue-6.3/series
@@ -279,3 +279,5 @@ ksmbd-fix-slab-out-of-bounds-read-in-smb2_handle_negotiate.patch
 ksmbd-fix-multiple-out-of-bounds-read-during-context-decoding.patch
 keys-asymmetric-copy-sig-and-digest-in-public_key_verify_signature.patch
 regmap-account-for-register-length-when-chunking.patch
+tpm-tpm_tis-request-threaded-interrupt-handler.patch
+iommu-amd-pgtbl_v2-fix-domain-max-address.patch

diff --git a/queue-6.3/tpm-tpm_tis-request-threaded-interrupt-handler.patch b/queue-6.3/tpm-tpm_tis-request-threaded-interrupt-handler.patch
new file mode 100644 (file)
index 0000000..bfff68c
--- /dev/null
+++ b/queue-6.3/tpm-tpm_tis-request-threaded-interrupt-handler.patch
@@ -0,0 +1,45 @@
+From 0c7e66e5fd69bf21034c9a9b081d7de7c3eb2cea Mon Sep 17 00:00:00 2001
+From: Lino Sanfilippo <l.sanfilippo@kunbus.com>
+Date: Thu, 24 Nov 2022 14:55:34 +0100
+Subject: tpm, tpm_tis: Request threaded interrupt handler
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Lino Sanfilippo <l.sanfilippo@kunbus.com>
+
+commit 0c7e66e5fd69bf21034c9a9b081d7de7c3eb2cea upstream.
+
+The TIS interrupt handler at least has to read and write the interrupt
+status register. In case of SPI both operations result in a call to
+tpm_tis_spi_transfer() which uses the bus_lock_mutex of the spi device
+and thus must only be called from a sleepable context.
+
+To ensure this request a threaded interrupt handler.
+
+Signed-off-by: Lino Sanfilippo <l.sanfilippo@kunbus.com>
+Tested-by: Michael Niewöhner <linux@mniewoehner.de>
+Tested-by: Jarkko Sakkinen <jarkko@kernel.org>
+Reviewed-by: Jarkko Sakkinen <jarkko@kernel.org>
+Signed-off-by: Jarkko Sakkinen <jarkko@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/char/tpm/tpm_tis_core.c |    7 +++++--
+ 1 file changed, 5 insertions(+), 2 deletions(-)
+
+--- a/drivers/char/tpm/tpm_tis_core.c
++++ b/drivers/char/tpm/tpm_tis_core.c
+@@ -805,8 +805,11 @@ static int tpm_tis_probe_irq_single(stru
+       int rc;
+       u32 int_status;
+ 
+-      if (devm_request_irq(chip->dev.parent, irq, tis_int_handler, flags,
+-                           dev_name(&chip->dev), chip) != 0) {
++
++      rc = devm_request_threaded_irq(chip->dev.parent, irq, NULL,
++                                     tis_int_handler, IRQF_ONESHOT | flags,
++                                     dev_name(&chip->dev), chip);
++      if (rc) {
+               dev_info(&chip->dev, "Unable to request irq: %d for probe\n",
+                        irq);
+               return -1;