clk: meson: meson8b: do not use cpu_div3 for cpu_scale_out_sel

[ Upstream commit a5ac1ead32c9aac285f6436e09b4f6111996e9b8 ]

The cpu_div3 clock (cpu_in divided by 3) generates a signal with a duty
cycle of 33%. The CPU clock however requires a clock signal with a duty
cycle of 50% to run stable.
cpu_div3 was observed to be problematic when cycling through all
available CPU frequencies (with additional patches on top of this one)
while running "stress --cpu 4" in the background. This caused sporadic
hangs where the whole system would fully lock up.

Amlogic's 3.10 kernel code also does not use the cpu_div3 clock either
when changing the CPU clock.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lkml.kernel.org/r/20181115224048.13511-3-martin.blumenstingl@googlemail.com
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
index 50060e895e7ad32e025b9547616d4a385f4c42c8..580a86d120e84e0b732537ad51e1dbc80f01b48c 100644 (file)
--- a/drivers/clk/meson/meson8b.c
+++ b/drivers/clk/meson/meson8b.c
@@ -596,20 +596,27 @@ static struct clk_regmap meson8b_cpu_scale_div = {
        },
 };
 
+static u32 mux_table_cpu_scale_out_sel[] = { 0, 1, 3 };
 static struct clk_regmap meson8b_cpu_scale_out_sel = {
        .data = &(struct clk_regmap_mux_data){
                .offset = HHI_SYS_CPU_CLK_CNTL0,
                .mask = 0x3,
                .shift = 2,
+               .table = mux_table_cpu_scale_out_sel,
        },
        .hw.init = &(struct clk_init_data){
                .name = "cpu_scale_out_sel",
                .ops = &clk_regmap_mux_ro_ops,
+               /*
+                * NOTE: We are skipping the parent with value 0x2 (which is
+                * "cpu_div3") because it results in a duty cycle of 33% which
+                * makes the system unstable and can result in a lockup of the
+                * whole system.
+                */
                .parent_names = (const char *[]) { "cpu_in_sel",
                                                   "cpu_div2",
-                                                  "cpu_div3",
                                                   "cpu_scale_div" },
-               .num_parents = 4,
+               .num_parents = 3,
                .flags = CLK_SET_RATE_PARENT,
        },
 };