--- /dev/null
+From 7ce67a38f799d1fb332f672b117efbadedaa5352 Mon Sep 17 00:00:00 2001
+From: Felipe Balbi <balbi@ti.com>
+Date: Fri, 2 Jan 2015 16:15:59 -0600
+Subject: net: ethernet: cpsw: fix hangs with interrupts
+
+From: Felipe Balbi <balbi@ti.com>
+
+commit 7ce67a38f799d1fb332f672b117efbadedaa5352 upstream.
+
+The CPSW IP implements pulse-signaled interrupts. Due to
+that we must write a correct, pre-defined value to the
+CPDMA_MACEOIVECTOR register so the controller generates
+a pulse on the correct IRQ line to signal the End Of
+Interrupt.
+
+The way the driver is written today, all four IRQ lines
+are requested using the same IRQ handler and, because of
+that, we could fall into situations where a TX IRQ fires
+but we tell the controller that we ended an RX IRQ (or
+vice-versa). This situation triggers an IRQ storm on the
+reserved IRQ 127 of INTC which will in turn call ack_bad_irq()
+which will, then, print a ton of:
+
+ unexpected IRQ trap at vector 00
+
+In order to fix the problem, we are moving all calls to
+cpdma_ctlr_eoi() inside the IRQ handler and making sure
+we *always* write the correct value to the CPDMA_MACEOIVECTOR
+register. Note that the algorithm assumes that IRQ numbers and
+value-to-be-written-to-EOI are proportional, meaning that a
+write of value 0 would trigger an EOI pulse for the RX_THRESHOLD
+Interrupt and that's the IRQ number sitting in the 0-th index
+of our irqs_table array.
+
+This, however, is safe at least for current implementations of
+CPSW so we will refrain from making the check smarter (and, as
+a side-effect, slower) until we actually have a platform where
+IRQ lines are swapped.
+
+This patch has been tested for several days with AM335x- and
+AM437x-based platforms. AM57x was left out because there are
+still pending patches to enable ethernet in mainline for that
+platform. A read of the TRM confirms the statement on previous
+paragraph.
+
+Reported-by: Yegor Yefremov <yegorslists@googlemail.com>
+Fixes: 510a1e7 (drivers: net: davinci_cpdma: acknowledge interrupt properly)
+Signed-off-by: Felipe Balbi <balbi@ti.com>
+Acked-by: Tony Lindgren <tony@atomide.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/net/ethernet/ti/cpsw.c | 19 ++++++++-----------
+ 1 file changed, 8 insertions(+), 11 deletions(-)
+
+--- a/drivers/net/ethernet/ti/cpsw.c
++++ b/drivers/net/ethernet/ti/cpsw.c
+@@ -757,6 +757,14 @@ requeue:
+ static irqreturn_t cpsw_interrupt(int irq, void *dev_id)
+ {
+ struct cpsw_priv *priv = dev_id;
++ int value = irq - priv->irqs_table[0];
++
++ /* NOTICE: Ending IRQ here. The trick with the 'value' variable above
++ * is to make sure we will always write the correct value to the EOI
++ * register. Namely 0 for RX_THRESH Interrupt, 1 for RX Interrupt, 2
++ * for TX Interrupt and 3 for MISC Interrupt.
++ */
++ cpdma_ctlr_eoi(priv->dma, value);
+
+ cpsw_intr_disable(priv);
+ if (priv->irq_enabled == true) {
+@@ -786,8 +794,6 @@ static int cpsw_poll(struct napi_struct
+ int num_tx, num_rx;
+
+ num_tx = cpdma_chan_process(priv->txch, 128);
+- if (num_tx)
+- cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
+
+ num_rx = cpdma_chan_process(priv->rxch, budget);
+ if (num_rx < budget) {
+@@ -795,7 +801,6 @@ static int cpsw_poll(struct napi_struct
+
+ napi_complete(napi);
+ cpsw_intr_enable(priv);
+- cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
+ prim_cpsw = cpsw_get_slave_priv(priv, 0);
+ if (prim_cpsw->irq_enabled == false) {
+ prim_cpsw->irq_enabled = true;
+@@ -1310,8 +1315,6 @@ static int cpsw_ndo_open(struct net_devi
+ napi_enable(&priv->napi);
+ cpdma_ctlr_start(priv->dma);
+ cpsw_intr_enable(priv);
+- cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
+- cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
+
+ prim_cpsw = cpsw_get_slave_priv(priv, 0);
+ if (prim_cpsw->irq_enabled == false) {
+@@ -1578,9 +1581,6 @@ static void cpsw_ndo_tx_timeout(struct n
+ cpdma_chan_start(priv->txch);
+ cpdma_ctlr_int_ctrl(priv->dma, true);
+ cpsw_intr_enable(priv);
+- cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
+- cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
+-
+ }
+
+ static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p)
+@@ -1620,9 +1620,6 @@ static void cpsw_ndo_poll_controller(str
+ cpsw_interrupt(ndev->irq, priv);
+ cpdma_ctlr_int_ctrl(priv->dma, true);
+ cpsw_intr_enable(priv);
+- cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
+- cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
+-
+ }
+ #endif
+
--- /dev/null
+From e86fb5e8ab95f10ec5f2e9430119d5d35020c951 Mon Sep 17 00:00:00 2001
+From: Long Li <longli@microsoft.com>
+Date: Fri, 5 Dec 2014 19:38:18 -0800
+Subject: storvsc: ring buffer failures may result in I/O freeze
+
+From: Long Li <longli@microsoft.com>
+
+commit e86fb5e8ab95f10ec5f2e9430119d5d35020c951 upstream.
+
+When ring buffer returns an error indicating retry, storvsc may not
+return a proper error code to SCSI when bounce buffer is not used.
+This has introduced I/O freeze on RAID running atop storvsc devices.
+This patch fixes it by always returning a proper error code.
+
+Signed-off-by: Long Li <longli@microsoft.com>
+Reviewed-by: K. Y. Srinivasan <kys@microsoft.com>
+Signed-off-by: Christoph Hellwig <hch@lst.de>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/scsi/storvsc_drv.c | 7 +++----
+ 1 file changed, 3 insertions(+), 4 deletions(-)
+
+--- a/drivers/scsi/storvsc_drv.c
++++ b/drivers/scsi/storvsc_drv.c
+@@ -1688,13 +1688,12 @@ static int storvsc_queuecommand(struct S
+ if (ret == -EAGAIN) {
+ /* no more space */
+
+- if (cmd_request->bounce_sgl_count) {
++ if (cmd_request->bounce_sgl_count)
+ destroy_bounce_buffer(cmd_request->bounce_sgl,
+ cmd_request->bounce_sgl_count);
+
+- ret = SCSI_MLQUEUE_DEVICE_BUSY;
+- goto queue_error;
+- }
++ ret = SCSI_MLQUEUE_DEVICE_BUSY;
++ goto queue_error;
+ }
+
+ return 0;
--- /dev/null
+From 280dbc572357eb50184663fc9e4aaf09c8141e9b Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Bj=C3=B8rn=20Mork?= <bjorn@mork.no>
+Date: Tue, 23 Dec 2014 12:57:43 +0100
+Subject: x86/build: Clean auto-generated processor feature files
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: =?UTF-8?q?Bj=C3=B8rn=20Mork?= <bjorn@mork.no>
+
+commit 280dbc572357eb50184663fc9e4aaf09c8141e9b upstream.
+
+Commit 9def39be4e96 ("x86: Support compiling out human-friendly
+processor feature names") made two source file targets
+conditional. Such conditional targets will not be cleaned
+automatically by make mrproper.
+
+Fix by adding explicit clean-files targets for the two files.
+
+Fixes: 9def39be4e96 ("x86: Support compiling out human-friendly processor feature names")
+Signed-off-by: Bjørn Mork <bjorn@mork.no>
+Cc: Josh Triplett <josh@joshtriplett.org>
+Link: http://lkml.kernel.org/r/1419335863-10608-1-git-send-email-bjorn@mork.no
+Signed-off-by: Ingo Molnar <mingo@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+diff --git a/arch/x86/boot/Makefile b/arch/x86/boot/Makefile
+index 5b016e2498f3..3db07f30636f 100644
+--- a/arch/x86/boot/Makefile
++++ b/arch/x86/boot/Makefile
+@@ -51,6 +51,7 @@ targets += cpustr.h
+ $(obj)/cpustr.h: $(obj)/mkcpustr FORCE
+ $(call if_changed,cpustr)
+ endif
++clean-files += cpustr.h
+
+ # ---------------------------------------------------------------------------
+
+diff --git a/arch/x86/kernel/cpu/Makefile b/arch/x86/kernel/cpu/Makefile
+index e27b49d7c922..80091ae54c2b 100644
+--- a/arch/x86/kernel/cpu/Makefile
++++ b/arch/x86/kernel/cpu/Makefile
+@@ -66,3 +66,4 @@ targets += capflags.c
+ $(obj)/capflags.c: $(cpufeature) $(src)/mkcapflags.sh FORCE
+ $(call if_changed,mkcapflags)
+ endif
++clean-files += capflags.c
projects / thirdparty / kernel / stable-queue.git / commitdiff
