pinctrl: renesas: r8a779g0: Fix IRQ suffixes

The suffixes of the IRQ identifiers for external interrupts 0-3
are inconsistent:
  - "IRQ0" and "IRQ0_A",
  - "IRQ1" and "IRQ1_A",
  - "IRQ2" and "IRQ2_A",
  - "IRQ3" and "IRQ3_B".
The suffixes for external interrupts 4 and 5 do follow conventional
naming:
  - "IRQ4A" and IRQ4_B",
  - "IRQ5".

Fix this by adopting R-Car V4M naming:
  - Rename "IRQ[0-2]_A" to "IRQ[0-2]_B",
  - Rename "IRQ[0-3]" to "IRQ[0-3]_A".

Fixes: ad9bb2fec66262b0 ("pinctrl: renesas: Initial R8A779G0 (R-Car V4H) PFC support")
Fixes: 1b23d8a478bea9d1 ("pinctrl: renesas: r8a779g0: Add missing IRQx_A/IRQx_B")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/8ce9baf0a0f9346544a3ac801fd962c7c12fd247.1717754960.git.geert+renesas@glider.be

diff --git a/drivers/pinctrl/renesas/pfc-r8a779g0.c b/drivers/pinctrl/renesas/pfc-r8a779g0.c
index e3c720ea76e32bd7d34c5bad8f30640d3eeb24d7..f9f650f232e6e71e19b775b51d58d72bd3e67c4f 100644 (file)
--- a/drivers/pinctrl/renesas/pfc-r8a779g0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779g0.c
@@ -68,10 +68,10 @@
 #define GPSR0_9                F_(MSIOF5_SYNC,         IP1SR0_7_4)
 #define GPSR0_8                F_(MSIOF5_SS1,          IP1SR0_3_0)
 #define GPSR0_7                F_(MSIOF5_SS2,          IP0SR0_31_28)
-#define GPSR0_6                F_(IRQ0,                IP0SR0_27_24)
-#define GPSR0_5                F_(IRQ1,                IP0SR0_23_20)
-#define GPSR0_4                F_(IRQ2,                IP0SR0_19_16)
-#define GPSR0_3                F_(IRQ3,                IP0SR0_15_12)
+#define GPSR0_6                F_(IRQ0_A,              IP0SR0_27_24)
+#define GPSR0_5                F_(IRQ1_A,              IP0SR0_23_20)
+#define GPSR0_4                F_(IRQ2_A,              IP0SR0_19_16)
+#define GPSR0_3                F_(IRQ3_A,              IP0SR0_15_12)
 #define GPSR0_2                F_(GP0_02,              IP0SR0_11_8)
 #define GPSR0_1                F_(GP0_01,              IP0SR0_7_4)
 #define GPSR0_0                F_(GP0_00,              IP0SR0_3_0)
@@ -278,10 +278,10 @@
 #define IP0SR0_3_0     F_(0, 0)                FM(ERROROUTC_N_B)       FM(TCLK2_A)             F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP0SR0_7_4     F_(0, 0)                FM(MSIOF3_SS1)          F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP0SR0_11_8    F_(0, 0)                FM(MSIOF3_SS2)          F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR0_15_12   FM(IRQ3)                FM(MSIOF3_SCK)          F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR0_19_16   FM(IRQ2)                FM(MSIOF3_TXD)          F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR0_23_20   FM(IRQ1)                FM(MSIOF3_RXD)          F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR0_27_24   FM(IRQ0)                FM(MSIOF3_SYNC)         F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR0_15_12   FM(IRQ3_A)              FM(MSIOF3_SCK)          F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR0_19_16   FM(IRQ2_A)              FM(MSIOF3_TXD)          F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR0_23_20   FM(IRQ1_A)              FM(MSIOF3_RXD)          F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR0_27_24   FM(IRQ0_A)              FM(MSIOF3_SYNC)         F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP0SR0_31_28   FM(MSIOF5_SS2)          F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 
 /* IP1SR0 */           /* 0 */                 /* 1 */                 /* 2 */                 /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
@@ -290,7 +290,7 @@
 #define IP1SR0_11_8    FM(MSIOF5_TXD)          F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP1SR0_15_12   FM(MSIOF5_SCK)          F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP1SR0_19_16   FM(MSIOF5_RXD)          F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR0_23_20   FM(MSIOF2_SS2)          FM(TCLK1)               FM(IRQ2_A)              F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR0_23_20   FM(MSIOF2_SS2)          FM(TCLK1)               FM(IRQ2_B)              F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP1SR0_27_24   FM(MSIOF2_SS1)          FM(HTX1_A)              FM(TX1_A)               F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP1SR0_31_28   FM(MSIOF2_SYNC)         FM(HRX1_A)              FM(RX1_A)               F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 
@@ -325,8 +325,8 @@
 #define IP2SR1_7_4     FM(SCIF_CLK)            FM(IRQ4_A)              F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP2SR1_11_8    FM(SSI_SCK)             FM(TCLK3)               F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP2SR1_15_12   FM(SSI_WS)              FM(TCLK4)               F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR1_19_16   FM(SSI_SD)              FM(IRQ0_A)              F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR1_23_20   FM(AUDIO_CLKOUT)        FM(IRQ1_A)              F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR1_19_16   FM(SSI_SD)              FM(IRQ0_B)              F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR1_23_20   FM(AUDIO_CLKOUT)        FM(IRQ1_B)              F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP2SR1_27_24   FM(AUDIO_CLKIN)         FM(PWM3_A)              F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP2SR1_31_28   F_(0, 0)                FM(TCLK2)               FM(MSIOF4_SS1)          FM(IRQ3_B)      F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 
@@ -724,16 +724,16 @@ static const u16 pinmux_data[] = {
 
        PINMUX_IPSR_GPSR(IP0SR0_11_8,   MSIOF3_SS2),
 
-       PINMUX_IPSR_GPSR(IP0SR0_15_12,  IRQ3),
+       PINMUX_IPSR_GPSR(IP0SR0_15_12,  IRQ3_A),
        PINMUX_IPSR_GPSR(IP0SR0_15_12,  MSIOF3_SCK),
 
-       PINMUX_IPSR_GPSR(IP0SR0_19_16,  IRQ2),
+       PINMUX_IPSR_GPSR(IP0SR0_19_16,  IRQ2_A),
        PINMUX_IPSR_GPSR(IP0SR0_19_16,  MSIOF3_TXD),
 
-       PINMUX_IPSR_GPSR(IP0SR0_23_20,  IRQ1),
+       PINMUX_IPSR_GPSR(IP0SR0_23_20,  IRQ1_A),
        PINMUX_IPSR_GPSR(IP0SR0_23_20,  MSIOF3_RXD),
 
-       PINMUX_IPSR_GPSR(IP0SR0_27_24,  IRQ0),
+       PINMUX_IPSR_GPSR(IP0SR0_27_24,  IRQ0_A),
        PINMUX_IPSR_GPSR(IP0SR0_27_24,  MSIOF3_SYNC),
 
        PINMUX_IPSR_GPSR(IP0SR0_31_28,  MSIOF5_SS2),
@@ -751,7 +751,7 @@ static const u16 pinmux_data[] = {
 
        PINMUX_IPSR_GPSR(IP1SR0_23_20,  MSIOF2_SS2),
        PINMUX_IPSR_GPSR(IP1SR0_23_20,  TCLK1),
-       PINMUX_IPSR_GPSR(IP1SR0_23_20,  IRQ2_A),
+       PINMUX_IPSR_GPSR(IP1SR0_23_20,  IRQ2_B),
 
        PINMUX_IPSR_GPSR(IP1SR0_27_24,  MSIOF2_SS1),
        PINMUX_IPSR_GPSR(IP1SR0_27_24,  HTX1_A),
@@ -851,10 +851,10 @@ static const u16 pinmux_data[] = {
        PINMUX_IPSR_GPSR(IP2SR1_15_12,  TCLK4),
 
        PINMUX_IPSR_GPSR(IP2SR1_19_16,  SSI_SD),
-       PINMUX_IPSR_GPSR(IP2SR1_19_16,  IRQ0_A),
+       PINMUX_IPSR_GPSR(IP2SR1_19_16,  IRQ0_B),
 
        PINMUX_IPSR_GPSR(IP2SR1_23_20,  AUDIO_CLKOUT),
-       PINMUX_IPSR_GPSR(IP2SR1_23_20,  IRQ1_A),
+       PINMUX_IPSR_GPSR(IP2SR1_23_20,  IRQ1_B),
 
        PINMUX_IPSR_GPSR(IP2SR1_27_24,  AUDIO_CLKIN),
        PINMUX_IPSR_GPSR(IP2SR1_27_24,  PWM3_A),