]> git.ipfire.org Git - thirdparty/glibc.git/commitdiff
x86: Fix Haswell strong flags (BZ#23709)
authorAdhemerval Zanella <adhemerval.zanella@linaro.org>
Thu, 11 Oct 2018 18:18:40 +0000 (15:18 -0300)
committerAdhemerval Zanella <adhemerval.zanella@linaro.org>
Tue, 23 Oct 2018 17:57:02 +0000 (14:57 -0300)
Th commit 'Disable TSX on some Haswell processors.' (2702856bf4) changed the
default flags for Haswell models.  Previously, new models were handled by the
default switch path, which assumed a Core i3/i5/i7 if AVX is available. After
the patch, Haswell models (0x3f, 0x3c, 0x45, 0x46) do not set the flags
Fast_Rep_String, Fast_Unaligned_Load, Fast_Unaligned_Copy, and
Prefer_PMINUB_for_stringop (only the TSX one).

This patch fixes it by disentangle the TSX flag handling from the memory
optimization ones.  The strstr case cited on patch now selects the
__strstr_sse2_unaligned as expected for the Haswell cpu.

Checked on x86_64-linux-gnu.

[BZ #23709]
* sysdeps/x86/cpu-features.c (init_cpu_features): Set TSX bits
independently of other flags.

ChangeLog
sysdeps/x86/cpu-features.c

index c0fbf75d23039880b321c2e0f3d80875d3a6fb76..c5fe2a8527602241c7693a1e4561a3d119fdb161 100644 (file)
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,9 @@
+2018-10-23  Adhemerval Zanella  <adhemerval.zanella@linaro.org>
+
+       [BZ #23709]
+       * sysdeps/x86/cpu-features.c (init_cpu_features): Set TSX bits
+       independently of other flags.
+
 2018-10-23  Florian Weimer  <fweimer@redhat.com>
 
        * time/tst-mktime2.c (N_STRINGS): Remove.
index f4e0f5a2eda1c948142dfeb87e9a55b4f707b21d..80b3054cf8a8700d949cbb3a514bcb8f3f953a65 100644 (file)
@@ -316,7 +316,13 @@ init_cpu_features (struct cpu_features *cpu_features)
                    | bit_arch_Fast_Unaligned_Copy
                    | bit_arch_Prefer_PMINUB_for_stringop);
              break;
+           }
 
+        /* Disable TSX on some Haswell processors to avoid TSX on kernels that
+           weren't updated with the latest microcode package (which disables
+           broken feature by default).  */
+        switch (model)
+           {
            case 0x3f:
              /* Xeon E7 v3 with stepping >= 4 has working TSX.  */
              if (stepping >= 4)