rs6000.c (rs6000_expand_vector_init): Remove unused variable "field".

2014-01-30  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

	* config/rs6000/rs6000.c (rs6000_expand_vector_init): Remove
	unused variable "field".
	* config/rs6000/vsx.md (vsx_mergel_<mode>): Add missing DONE.
	(vsx_mergeh_<mode>): Likewise.
	* config/rs6000/altivec.md (altivec_vmrghb): Likewise.
	(altivec_vmrghh): Likewise.
	(altivec_vmrghw): Likewise.
	(altivec_vmrglb): Likewise.
	(altivec_vmrglh): Likewise.
	(altivec_vmrglw): Likewise.
	(altivec_vspltb): Add missing uses.
	(altivec_vsplth): Likewise.
	(altivec_vspltw): Likewise.
	(altivec_vspltsf): Likewise.

From-SVN: r207326

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index d78cf54375d9fb9eb0b20fa7722e5ce1569e79f1..8939e12abdc19068e7e4c06e1b310251137759a2 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,20 @@
+2014-01-30  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
+
+       * config/rs6000/rs6000.c (rs6000_expand_vector_init): Remove
+       unused variable "field".
+       * config/rs6000/vsx.md (vsx_mergel_<mode>): Add missing DONE.
+       (vsx_mergeh_<mode>): Likewise.
+       * config/rs6000/altivec.md (altivec_vmrghb): Likewise.
+       (altivec_vmrghh): Likewise.
+       (altivec_vmrghw): Likewise.
+       (altivec_vmrglb): Likewise.
+       (altivec_vmrglh): Likewise.
+       (altivec_vmrglw): Likewise.
+       (altivec_vspltb): Add missing uses.
+       (altivec_vsplth): Likewise.
+       (altivec_vspltw): Likewise.
+       (altivec_vspltsf): Likewise.
+
 2014-01-30  Jakub Jelinek  <jakub@redhat.com>
 
        PR target/59923

diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index aacd3fbc0d6f7be27ca3448beb2de272d6f74e0d..7e92d06888f42bb47e90a5030c4b06f6817765c3 100644 (file)
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -871,6 +871,7 @@
 
   x = gen_rtx_VEC_SELECT (V16QImode, x, gen_rtx_PARALLEL (VOIDmode, v));
   emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
+  DONE;
 })
 
 (define_insn "*altivec_vmrghb_internal"
@@ -930,6 +931,7 @@
 
   x = gen_rtx_VEC_SELECT (V8HImode, x, gen_rtx_PARALLEL (VOIDmode, v));
   emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
+  DONE;
 })
 
 (define_insn "*altivec_vmrghh_internal"
@@ -983,6 +985,7 @@
 
   x = gen_rtx_VEC_SELECT (V4SImode, x, gen_rtx_PARALLEL (VOIDmode, v));
   emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
+  DONE;
 })
 
 (define_insn "*altivec_vmrghw_internal"
@@ -1057,6 +1060,7 @@
 
   x = gen_rtx_VEC_SELECT (V16QImode, x, gen_rtx_PARALLEL (VOIDmode, v));
   emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
+  DONE;
 })
 
 (define_insn "*altivec_vmrglb_internal"
@@ -1116,6 +1120,7 @@
 
   x = gen_rtx_VEC_SELECT (V8HImode, x, gen_rtx_PARALLEL (VOIDmode, v));
   emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
+  DONE;
 })
 
 (define_insn "*altivec_vmrglh_internal"
@@ -1169,6 +1174,7 @@
 
   x = gen_rtx_VEC_SELECT (V4SImode, x, gen_rtx_PARALLEL (VOIDmode, v));
   emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
+  DONE;
 })
 
 (define_insn "*altivec_vmrglw_internal"
@@ -1601,9 +1607,9 @@
   [(set_attr "type" "veccomplex")])
 
 (define_expand "altivec_vspltb"
-  [(match_operand:V16QI 0 "register_operand" "")
-   (match_operand:V16QI 1 "register_operand" "")
-   (match_operand:QI 2 "u5bit_cint_operand" "")]
+  [(use (match_operand:V16QI 0 "register_operand" ""))
+   (use (match_operand:V16QI 1 "register_operand" ""))
+   (use (match_operand:QI 2 "u5bit_cint_operand" ""))]
   "TARGET_ALTIVEC"
 {
   rtvec v;
@@ -1649,9 +1655,9 @@
   [(set_attr "type" "vecperm")])
 
 (define_expand "altivec_vsplth"
-  [(match_operand:V8HI 0 "register_operand" "")
-   (match_operand:V8HI 1 "register_operand" "")
-   (match_operand:QI 2 "u5bit_cint_operand" "")]
+  [(use (match_operand:V8HI 0 "register_operand" ""))
+   (use (match_operand:V8HI 1 "register_operand" ""))
+   (use (match_operand:QI 2 "u5bit_cint_operand" ""))]
   "TARGET_ALTIVEC"
 {
   rtvec v;
@@ -1697,9 +1703,9 @@
   [(set_attr "type" "vecperm")])
 
 (define_expand "altivec_vspltw"
-  [(match_operand:V4SI 0 "register_operand" "")
-   (match_operand:V4SI 1 "register_operand" "")
-   (match_operand:QI 2 "u5bit_cint_operand" "")]
+  [(use (match_operand:V4SI 0 "register_operand" ""))
+   (use (match_operand:V4SI 1 "register_operand" ""))
+   (use (match_operand:QI 2 "u5bit_cint_operand" ""))]
   "TARGET_ALTIVEC"
 {
   rtvec v;
@@ -1745,9 +1751,9 @@
   [(set_attr "type" "vecperm")])
 
 (define_expand "altivec_vspltsf"
-  [(match_operand:V4SF 0 "register_operand" "")
-   (match_operand:V4SF 1 "register_operand" "")
-   (match_operand:QI 2 "u5bit_cint_operand" "")]
+  [(use (match_operand:V4SF 0 "register_operand" ""))
+   (use (match_operand:V4SF 1 "register_operand" ""))
+   (use (match_operand:QI 2 "u5bit_cint_operand" ""))]
   "TARGET_ALTIVEC"
 {
   rtvec v;

diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index ec5f5bf1beabb9a0c1df3d69541eedbe6ec5261c..0bd92d4352234b909d7647f1777990624e2d0d41 100644 (file)
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -5511,7 +5511,6 @@ rs6000_expand_vector_init (rtx target, rtx vals)
      of 64-bit items is not supported on Altivec.  */
   if (all_same && GET_MODE_SIZE (inner_mode) <= 4)
     {
-      rtx field;
       mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode));
       emit_move_insn (adjust_address_nv (mem, inner_mode, 0),
                      XVECEXP (vals, 0, 0));

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index c6d558ad6157d124fc608a3b31ea09d15773fa58..d0fc8cb7c9b8a660cde38f7c2b2f366a9755dd6b 100644 (file)
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -1701,6 +1701,7 @@
 
   x = gen_rtx_VEC_SELECT (<MODE>mode, x, gen_rtx_PARALLEL (VOIDmode, v));
   emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
+  DONE;
 })
 
 (define_expand "vsx_mergeh_<mode>"
@@ -1726,6 +1727,7 @@
 
   x = gen_rtx_VEC_SELECT (<MODE>mode, x, gen_rtx_PARALLEL (VOIDmode, v));
   emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
+  DONE;
 })
 
 ;; V2DF/V2DI splat