EDAC, i10nm: Check ECC enabling status per channel

The i10nm_edac only checks the ECC enabling status for the first
channel of the memory controller. If there aren't memory DIMMs
populated on the first channel, but at least one DIMM populated
on the second channel, it will wrongly report that the ECC for
the memory controller is disabled that fails to load the i10nm_edac
driver. Fix it by checking ECC enabling status per channel.

[Tony: Also report which channel has ECC disabled]

Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>

diff --git a/drivers/edac/i10nm_base.c b/drivers/edac/i10nm_base.c
index 48c6cecc96833ebc3862ef2c519f47121f81d9f1..72cc20a90ac1b3009d7af1b21787c84316b54d26 100644 (file)
--- a/drivers/edac/i10nm_base.c
+++ b/drivers/edac/i10nm_base.c
@@ -168,9 +168,9 @@ static int i10nm_get_dimm_config(struct mem_ctl_info *mci)
                                ndimms += skx_get_nvdimm_info(dimm, imc, i, j,
                                                              EDAC_MOD_STR);
                }
-               if (ndimms && !i10nm_check_ecc(imc, 0)) {
-                       i10nm_printk(KERN_ERR, "ECC is disabled on imc %d\n",
-                                    imc->mc);
+               if (ndimms && !i10nm_check_ecc(imc, i)) {
+                       i10nm_printk(KERN_ERR, "ECC is disabled on imc %d channel %d\n",
+                                    imc->mc, i);
                        return -ENODEV;
                }
        }