Merge tag 'riscv-cache-for-v6.18' of https://git.kernel.org/pub/scm/linux/kernel...

RISC-V cache drivers for v6.18

sifive:
Reduce the number of fences issued while flushing. Samuel reports that
this is approximately a 15% speed-up.

ax45mp:
Fix the binding so that it permits the cache-sets setting used by the
recently added QiLai SoC.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
* tag 'riscv-cache-for-v6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
  cache: sifive_ccache: Optimize cache flushes
  dt-bindings: cache: ax45mp: add 2048 as a supported cache-sets value

Link: https://lore.kernel.org/r/20250924-relenting-aqua-a4a93b89809e@spud
Signed-off-by: Arnd Bergmann <arnd@arndb.de>